OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Error creating feed file, please check write permissions.
openmsp430 WebSVN RSS feed - openmsp430 https://opencores.org/websvn//websvn/listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F& Fri, 29 Mar 2024 05:01:43 +0100 FeedCreator 1.7.2 Major verificaiton and benchmark update to support both MSPGCC ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=200 <div><strong>Rev 200 - olivier.girard</strong> (99 file(s) modified)</div><div>Major verificaiton and benchmark update to support both MSPGCC ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />- /openmsp430/trunk/core/synthesis/synopsys/results<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/tmp<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/_xmsgs<br />+ /openmsp430/trunk/doc/toolchain_benchmark.txt<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />- /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/xlnx_auto_0_xdb<br />- /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v<br />- /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/tmp<br />- /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br /> olivier.girard Wed, 21 Jan 2015 22:01:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=200 Update hardware breakpoint unit with the followings: - fixed hardware breakpoint ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=175 <div><strong>Rev 175 - olivier.girard</strong> (14 file(s) modified)</div><div>Update hardware breakpoint unit with the followings:<br /> - fixed hardware breakpoint ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br /> olivier.girard Wed, 30 Jan 2013 21:21:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=175 Add some SVN ignore patterns https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=139 <div><strong>Rev 139 - olivier.girard</strong> (2 file(s) modified)</div><div>Add some SVN ignore patterns</div>~ /openmsp430/trunk/core/synthesis/synopsys<br />~ /openmsp430/trunk/core/synthesis/synopsys/results<br /> olivier.girard Mon, 23 Apr 2012 11:16:52 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=139 Add full ASIC support (low-power modes, DFT, ...). Improved serial debug ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=134 <div><strong>Rev 134 - olivier.girard</strong> (116 file(s) modified)</div><div>Add full ASIC support (low-power modes, DFT, ...).<br /> Improved serial debug ...</div>~ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v<br />~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/registers.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />- /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/template.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/load_waveform.sav<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/core.f<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/scan.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/scan.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/submit.prj<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v<br />~ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/run_tmax<br />~ /openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/tmax.tcl<br />~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br /> olivier.girard Thu, 22 Mar 2012 20:31:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=134 Re-organized the &quot;openMSP430_defines.v&quot; file. ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=111 <div><strong>Rev 111 - olivier.girard</strong> (185 file(s) modified)</div><div>Re-organized the &quot;openMSP430_defines.v&quot; file.<br /> Re-defined the CPU_ID register of the debug ...</div>~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43<br />~ /openmsp430/trunk/core/synthesis/actel/design_files.v<br />~ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/altera_de1_board/synthesis/altera/openMSP430_fpga_top.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_gpio.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/openMSP430_fpga.prj<br /> olivier.girard Fri, 20 May 2011 20:39:02 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=111 Update all bash scripts headers with &quot;#!/bin/bash&quot; instead of ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=73 <div><strong>Rev 73 - olivier.girard</strong> (12 file(s) modified)</div><div>Update all bash scripts headers with &quot;#!/bin/bash&quot; instead of &quot;#!/bin/sh&quot;.<br /> This ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/synthesis/synopsys/run_syn<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/load_pmem.sh<br /> olivier.girard Tue, 03 Aug 2010 19:26:39 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=73 Update synthesis scripts with the hardware multiplier support. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=68 <div><strong>Rev 68 - olivier.girard</strong> (15 file(s) modified)</div><div>Update synthesis scripts with the hardware multiplier support.</div>+ /openmsp430/trunk/core/synthesis/actel/run_analysis.mpy.log<br />~ /openmsp430/trunk/core/synthesis/actel/run_analysis.tcl<br />~ /openmsp430/trunk/core/synthesis/altera<br />~ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />+ /openmsp430/trunk/core/synthesis/altera/run_analysis.area.mpy.log<br />+ /openmsp430/trunk/core/synthesis/altera/run_analysis.speed.mpy.log<br />~ /openmsp430/trunk/core/synthesis/altera/run_analysis.tcl<br />~ /openmsp430/trunk/core/synthesis/altera/src/megawizard<br />~ /openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v<br />~ /openmsp430/trunk/core/synthesis/xilinx<br />~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br />+ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.area.mpy.log<br />+ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.speed.mpy.log<br />~ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.tcl<br />~ /openmsp430/trunk/core/synthesis/xilinx/src/openMSP430_defines.v<br /> olivier.girard Sun, 07 Mar 2010 12:01:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=68 Add Actel synthesis environment for size and speed analysis. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=64 <div><strong>Rev 64 - olivier.girard</strong> (27 file(s) modified)</div><div>Add Actel synthesis environment for size and speed analysis.</div>+ /openmsp430/trunk/core/synthesis/actel<br />+ /openmsp430/trunk/core/synthesis/actel/design_files.sdc<br />+ /openmsp430/trunk/core/synthesis/actel/design_files.v<br />+ /openmsp430/trunk/core/synthesis/actel/libero_designer.tcl<br />+ /openmsp430/trunk/core/synthesis/actel/run_analysis.log<br />+ /openmsp430/trunk/core/synthesis/actel/run_analysis.tcl<br />+ /openmsp430/trunk/core/synthesis/actel/src<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_alu.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_clock_module.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_dbg.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_dbg_hwbrk.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_dbg_uart.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_execution_unit.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_frontend.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_mem_backbone.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_register_file.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_sfr.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/omsp_watchdog.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/openMSP430.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/openMSP430_defines.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/openMSP430_fpga.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/openMSP430_undefines.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/smartgen<br />+ /openmsp430/trunk/core/synthesis/actel/src/smartgen/dmem.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/smartgen/pmem.v<br />+ /openmsp430/trunk/core/synthesis/actel/src/timescale.v<br />+ /openmsp430/trunk/core/synthesis/actel/synplify.tcl<br /> olivier.girard Sun, 14 Feb 2010 12:06:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=64 Add Altera synthesis environment for size and speed analysis. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=63 <div><strong>Rev 63 - olivier.girard</strong> (29 file(s) modified)</div><div>Add Altera synthesis environment for size and speed analysis.</div>+ /openmsp430/trunk/core/synthesis/altera<br />+ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />+ /openmsp430/trunk/core/synthesis/altera/openMSP430_fpga.tcl<br />+ /openmsp430/trunk/core/synthesis/altera/run_analysis.area.log<br />+ /openmsp430/trunk/core/synthesis/altera/run_analysis.speed.log<br />+ /openmsp430/trunk/core/synthesis/altera/run_analysis.tcl<br />+ /openmsp430/trunk/core/synthesis/altera/src<br />+ /openmsp430/trunk/core/synthesis/altera/src/arch.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/arria2gx_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/arriagx_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone2_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone3_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix2_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix3_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_dmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/megawizard/stratix_pmem.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/openMSP430_defines.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/openMSP430_fpga.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/openMSP430_undefines.v<br />+ /openmsp430/trunk/core/synthesis/altera/src/timescale.v<br /> olivier.girard Sun, 14 Feb 2010 11:58:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=63 Add Xilinx synthesis environment for size&amp;speed analysis. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=62 <div><strong>Rev 62 - olivier.girard</strong> (246 file(s) modified)</div><div>Add Xilinx synthesis environment for size&amp;speed analysis.</div>+ /openmsp430/trunk/core/synthesis/xilinx<br />+ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br />+ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.ucf<br />+ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.area.log<br />+ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.speed.log<br />+ /openmsp430/trunk/core/synthesis/xilinx/run_analysis.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/arch.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/.lso<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/blk_mem_gen_ds512.pdf<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/coregen.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/coregen.log<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.asy<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.sym<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.vhd<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.vho<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.asy<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.sym<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.vhd<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.vho<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.asy<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.vhd<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.vho<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/tmp/_cg<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4lx.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6.cgp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.asy<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.vhd<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.vho<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.asy<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.gise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.ise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.ngc<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.veo<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.vhd<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.vho<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.xco<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem.xise<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_flist.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_readme.txt<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xdb<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xdb/tmp<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xmdf.tcl<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/coregen/_xmsgs<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/openMSP430_defines.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/openMSP430_fpga.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/openMSP430_undefines.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/src/timescale.v<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan3.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan3a.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan3adsp.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan3e.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan6.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_virtex4.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_virtex5.opt<br />+ /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_virtex6.opt<br /> olivier.girard Sun, 14 Feb 2010 09:57:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=62 Update Design Compiler Synthesis scripts. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=56 <div><strong>Rev 56 - olivier.girard</strong> (4 file(s) modified)</div><div>Update Design Compiler Synthesis scripts.</div>~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/library.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl<br /> olivier.girard Thu, 28 Jan 2010 16:09:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=56 Upload complete openMSP430 project to the SVN repository https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=2 <div><strong>Rev 2 - olivier.girard</strong> (301 file(s) modified)</div><div>Upload complete openMSP430 project to the SVN repository</div>+ /openmsp430/trunk/core<br />+ /openmsp430/trunk/core/bench<br />+ /openmsp430/trunk/core/bench/verilog<br />+ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v<br />+ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />+ /openmsp430/trunk/core/bench/verilog/ram.v<br />+ /openmsp430/trunk/core/bench/verilog/registers.v<br />+ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />+ /openmsp430/trunk/core/doc<br />+ /openmsp430/trunk/core/doc/slau049f.pdf<br />+ /openmsp430/trunk/core/rtl<br />+ /openmsp430/trunk/core/rtl/verilog<br />+ /openmsp430/trunk/core/rtl/verilog/alu.v<br />+ /openmsp430/trunk/core/rtl/verilog/clock_module.v<br />+ /openmsp430/trunk/core/rtl/verilog/dbg.v<br />+ /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v<br />+ /openmsp430/trunk/core/rtl/verilog/dbg_uart.v<br />+ /openmsp430/trunk/core/rtl/verilog/execution_unit.v<br />+ /openmsp430/trunk/core/rtl/verilog/frontend.v<br />+ /openmsp430/trunk/core/rtl/verilog/mem_backbone.v<br />+ /openmsp430/trunk/core/rtl/verilog/openMSP430.inc<br />+ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph<br />+ /openmsp430/trunk/core/rtl/verilog/periph/gpio.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />+ /openmsp430/trunk/core/rtl/verilog/periph/timerA.v<br />+ /openmsp430/trunk/core/rtl/verilog/register_file.v<br />+ /openmsp430/trunk/core/rtl/verilog/sfr.v<br />+ /openmsp430/trunk/core/rtl/verilog/watchdog.v<br />+ /openmsp430/trunk/core/sim<br />+ /openmsp430/trunk/core/sim/rtl_sim<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/ihex2mem.tcl<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />+ /openmsp430/trunk/core/sim/rtl_sim/run<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/load_waveform.sav<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble<br />+ /openmsp430/trunk/core/sim/rtl_sim/src<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jc.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jc.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jeq.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jeq.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jge.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jge.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jl.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jl.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jmp.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jmp.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jn.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jn.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jnc.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jnc.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jne.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/c-jump_jne.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_addc.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_addc.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_and.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_and.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bis.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bis.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bit.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_bit.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_cmp.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_cmp.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_dadd.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_dadd.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_sub.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_sub.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_subc.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_subc.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_xor.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_xor.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />+ /openmsp430/trunk/core/synthesis<br />+ /openmsp430/trunk/core/synthesis/synopsys<br />+ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/library.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/results<br />+ /openmsp430/trunk/core/synthesis/synopsys/run_syn<br />+ /openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl<br />+ /openmsp430/trunk/fpga<br />+ /openmsp430/trunk/fpga/diligent_s3board<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench/verilog<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench/verilog/glbl.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench/verilog/msp_debug.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench/verilog/registers.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/bench/verilog/tb_openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/doc<br />+ /openmsp430/trunk/fpga/diligent_s3board/doc/board_user_guide.pdf<br />+ /openmsp430/trunk/fpga/diligent_s3board/doc/msp430f1121a.pdf<br />+ /openmsp430/trunk/fpga/diligent_s3board/doc/xapp462.pdf<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/coregen.log<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.asy<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.ngc<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.sym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.veo<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.xco<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_flist.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_readme.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_hi_xmdf.tcl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.asy<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.ngc<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.sym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.veo<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo.xco<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_flist.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_readme.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/ram_8x512_lo_xmdf.tcl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.asy<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.ngc<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.veo<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.xco<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_flist.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_readme.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi_xmdf.tcl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.asy<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.ngc<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.sym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.veo<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo.xco<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_flist.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_readme.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/rom_8x2k_lo_xmdf.tcl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/tmp<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/tmp/_cg<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0.ise<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise.lock<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/Autonym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/common<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/STE<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/_ProjRepoInternal_<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/Autonym<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/common<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/ngcbuild<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/driver_7segment.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/io_mux.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430.inc<br />+ /openmsp430/trunk/fpga/diligent_s3board/rtl/verilog/openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin/ihex2mem.tcl<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin/msp430sim<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/bin/rtlsim.sh<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/run<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/run/run<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/run/run_disassemble<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src/leds.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src/submit.f<br />+ /openmsp430/trunk/fpga/diligent_s3board/sim/rtl_sim/src/ta_uart.v<br />+ /openmsp430/trunk/fpga/diligent_s3board/software<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds/7seg.c<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds/7seg.h<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds/hardware.h<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds/main.c<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/leds/makefile<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/fll.h<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/fll.s<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/hardware.h<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/main.c<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/makefile<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/miniterm.py<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/README.txt<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/swuart.h<br />+ /openmsp430/trunk/fpga/diligent_s3board/software/ta_uart/swuart.s<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/create_bitstream<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/load_rom<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/memory.bmm<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.ucf<br />+ /openmsp430/trunk/fpga/diligent_s3board/synthesis/xilinx/openMSP430_fpga_top.v<br />+ /openmsp430/trunk/tools<br />+ /openmsp430/trunk/tools/bin<br />+ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.exe<br />+ /openmsp430/trunk/tools/bin/openmsp430-gdbproxy.tcl<br />+ /openmsp430/trunk/tools/bin/openmsp430-loader.exe<br />+ /openmsp430/trunk/tools/bin/openmsp430-loader.tcl<br />+ /openmsp430/trunk/tools/bin/openmsp430-minidebug.exe<br />+ /openmsp430/trunk/tools/bin/openmsp430-minidebug.tcl<br />+ /openmsp430/trunk/tools/freewrap642<br />+ /openmsp430/trunk/tools/freewrap642/freewrap.exe<br />+ /openmsp430/trunk/tools/freewrap642/freewrapTCLSH.exe<br />+ /openmsp430/trunk/tools/freewrap642/generate_exec.bat<br />+ /openmsp430/trunk/tools/freewrap642/tclpip85s.dll<br />+ /openmsp430/trunk/tools/lib<br />+ /openmsp430/trunk/tools/lib/tcl-lib<br />+ /openmsp430/trunk/tools/lib/tcl-lib/combobox.tcl<br />+ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl<br />+ /openmsp430/trunk/tools/lib/tcl-lib/dbg_uart.tcl<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/commands.tcl<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/doc<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/doc/ew_GDB_RSP.pdf<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/doc/Howto-GDB_Remote_Serial_Protocol.pdf<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/openmsp430-gdbproxy.tcl<br />+ /openmsp430/trunk/tools/openmsp430-gdbproxy/server.tcl<br /> olivier.girard Tue, 30 Jun 2009 21:26:49 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsynthesis%2F&rev=2
© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.