OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Error creating feed file, please check write permissions.
openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2F& Mon, 20 Apr 2026 12:23:24 +0100 FeedCreator 1.7.2 or1200: the infamous l.rfe fix, and bug fix for when ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=644 <div><strong>Rev 644 - julius</strong> (2 file(s) modified)</div><div>or1200: the infamous l.rfe fix, and bug fix for when ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:56:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=644 or1200: new ALU comparision implementation option, TLB invalidate register indicated ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=643 <div><strong>Rev 643 - julius</strong> (4 file(s) modified)</div><div>or1200: new ALU comparision implementation option, TLB invalidate register indicated ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rf.v<br /> julius Thu, 01 Sep 2011 18:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=643 or1200: add carry, overflow bits, and range exception https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=642 <div><strong>Rev 642 - julius</strong> (6 file(s) modified)</div><div>or1200: add carry, overflow bits, and range exception</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br /> julius Thu, 01 Sep 2011 18:49:24 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=642 or1200: fix serial multiply/divide bug https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=641 <div><strong>Rev 641 - julius</strong> (1 file(s) modified)</div><div>or1200: fix serial multiply/divide bug</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:47:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=641 or1200: add l.ext instructions, fix a MAC bug https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=640 <div><strong>Rev 640 - julius</strong> (6 file(s) modified)</div><div>or1200: add l.ext instructions, fix a MAC bug</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:43:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=640 or1200: or1200_dpram.v change task set_gpr to function https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=639 <div><strong>Rev 639 - julius</strong> (1 file(s) modified)</div><div>or1200: or1200_dpram.v change task set_gpr to function</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v<br /> julius Thu, 01 Sep 2011 18:36:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=639 orpsoc: xilinx: use XILINX env variable instead of rely on custom ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=638 <div><strong>Rev 638 - stekern</strong> (9 file(s) modified)</div><div>orpsoc: xilinx: use XILINX env variable<br /> <br /> instead of rely on custom ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br /> stekern Mon, 29 Aug 2011 03:19:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=638 porint parallel port(gpio) management task https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=637 <div><strong>Rev 637 - filepang</strong> (1 file(s) modified)</div><div>porint parallel port(gpio) management task</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/ParTest/ParTest.c<br /> filepang Fri, 26 Aug 2011 14:38:07 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=637 porting serial port management task, interrupt hander https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=636 <div><strong>Rev 636 - filepang</strong> (1 file(s) modified)</div><div>porting serial port management task, interrupt hander</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/serial/serial.c<br /> filepang Fri, 26 Aug 2011 14:36:02 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=636 Patch for http://bugzilla.opencores.org/show_bug.cgi?id=69. * ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=635 <div><strong>Rev 635 - jeremybennett</strong> (2 file(s) modified)</div><div>Patch for <a href="http://bugzilla.opencores.org/show_bug.cgi?id=69" target="_blank">http://bugzilla.opencores.org/show_bug.cgi?id=69</a>.<br /> <br /> * ...</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/linux-elf.h<br /> jeremybennett Thu, 25 Aug 2011 10:51:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=635 orpsoc: atlys: autoregenerate coregen cores Instead of keeping binary .ngc files ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=634 <div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br /> <br /> Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br /> stekern Wed, 24 Aug 2011 03:28:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=634 orpsoc: add Digilent Atlys spartan6 board README Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=633 <div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br /> stekern Wed, 24 Aug 2011 03:28:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=633 orpsoc: add Digilent Atlys spartan6 board sw include file Signed-off-by: Stefan ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=632 <div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br /> <br /> Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br /> stekern Wed, 24 Aug 2011 03:28:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=632 orpsoc: add Digilent Atlys spartan6 board testbench Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=631 <div><strong>Rev 631 - stekern</strong> (12 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board testbench<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v<br /> stekern Wed, 24 Aug 2011 03:28:24 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=631 orpsoc: add Digilent Atlys spartan6 board backend Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=630 <div><strong>Rev 630 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board backend<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf<br /> stekern Wed, 24 Aug 2011 03:28:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=630 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration Signed-off-by: Stefan ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=629 <div><strong>Rev 629 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board or1ksim configuration<br /> <br /> Signed-off-by: Stefan Kristiansson ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg<br /> stekern Wed, 24 Aug 2011 03:28:14 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=629 orpsoc: add Digilent Atlys spartan6 board Makefiles Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=628 <div><strong>Rev 628 - stekern</strong> (22 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board Makefiles<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile<br /> stekern Wed, 24 Aug 2011 03:28:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=628 orpsoc: add Digilent Atlys spartan6 board rtl Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=627 <div><strong>Rev 627 - stekern</strong> (42 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board rtl<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v<br /> stekern Wed, 24 Aug 2011 03:28:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=627 Fix to support GCC 4.6 by disabling -Werror. https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=626 <div><strong>Rev 626 - jeremybennett</strong> (1 file(s) modified)</div><div>Fix to support GCC 4.6 by disabling -Werror.</div>~ /openrisc/trunk/gnu-src/bld-all.sh<br /> jeremybennett Mon, 15 Aug 2011 12:36:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=626 Fixed configuration to work with GCC 4.6, added -Werror to ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=625 <div><strong>Rev 625 - jeremybennett</strong> (83 file(s) modified)</div><div>Fixed configuration to work with GCC 4.6, added -Werror to ...</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/pcu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/pcu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br /> jeremybennett Mon, 15 Aug 2011 11:44:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=625

Browse

Tools