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            <title>Fixed error message in Makefile</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=682</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 682 - skrzyp&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed error message in Makefile&lt;/div&gt;~ /openrisc/trunk/or_debug_proxy/Makefile&lt;br /&gt;</description>
            <author>skrzyp</author>
            <pubDate>Thu, 01 Mar 2012 09:51:50 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=682</guid>
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            <title>Updated to reflect latest scripts and creation of separate directory ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=681</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 681 - jeremybennett&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated to reflect latest scripts and creation of separate directory ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/README&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 29 Feb 2012 19:20:33 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=681</guid>
        </item>
        <item>
            <title>New directory structure for development tool chain tracking upstream mainline.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=680</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 680 - jeremybennett&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;New directory structure for development tool chain tracking upstream mainline.&lt;/div&gt;+ /openrisc/trunk/gnu-dev&lt;br /&gt;+ /openrisc/trunk/gnu-dev/or1k-gcc&lt;br /&gt;+ /openrisc/trunk/gnu-dev/or1k-src&lt;br /&gt;+ /openrisc/trunk/gnu-dev/README&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 29 Feb 2012 19:19:51 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=680</guid>
        </item>
        <item>
            <title>Allow setting the boot address as an external
parameter. If no ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=679</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 679 - olof&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;Allow setting the boot address as an external&lt;br /&gt;
parameter. If no ...&lt;/div&gt;~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v&lt;br /&gt;~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v&lt;br /&gt;~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v&lt;br /&gt;~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v&lt;br /&gt;</description>
            <author>olof</author>
            <pubDate>Wed, 29 Feb 2012 18:04:38 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=679</guid>
        </item>
        <item>
            <title>added credits</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=678</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 678 - skrzyp&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;added credits&lt;/div&gt;~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/v3_0/src/context.S&lt;br /&gt;</description>
            <author>skrzyp</author>
            <pubDate>Wed, 29 Feb 2012 14:51:46 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=678</guid>
        </item>
        <item>
            <title>atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=677</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 677 - stekern&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;atlys: add 2-clock synchronizer chain for ddr2_calib_done&lt;br /&gt;
&lt;br /&gt;
The signal ddr2_calib_done signal ...&lt;/div&gt;~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v&lt;br /&gt;</description>
            <author>stekern</author>
            <pubDate>Tue, 21 Feb 2012 16:01:04 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=677</guid>
        </item>
        <item>
            <title>Add a libgloss definition file for the new ORSoC OpenRISC ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=676</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 676 - olof&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Add a libgloss definition file for the new ORSoC OpenRISC ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/Makefile.in&lt;br /&gt;+ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/ordb2a.S&lt;br /&gt;</description>
            <author>olof</author>
            <pubDate>Mon, 13 Feb 2012 10:02:10 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=676</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 Source cleanup
 Add redzone beyond the stack pointer</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=675</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 675 - filepang&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 Source cleanup&lt;br /&gt;
 Add redzone beyond the stack pointer&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/reset.S&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portmacro.h&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Sat, 21 Jan 2012 22:47:14 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=675</guid>
        </item>
        <item>
            <title>or1200: Fix for Bug 76 - Incorrect unsigned integer less-than ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=674</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 674 - julius&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;or1200: Fix for Bug 76 - Incorrect unsigned integer less-than ...&lt;/div&gt;~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Wed, 18 Jan 2012 09:34:35 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=674</guid>
        </item>
        <item>
            <title>Multiple 64-bit fixes (mostly sign and size of constants). Fix ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=673</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 673 - yannv&lt;/strong&gt; (13 file(s) modified)&lt;/div&gt;&lt;div&gt;Multiple 64-bit fixes (mostly sign and size of constants). Fix ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-opc.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-opc.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-opc.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-opc.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-opc.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/or32.c&lt;br /&gt;~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-dis.c&lt;br /&gt;~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-opc.c&lt;br /&gt;</description>
            <author>yannv</author>
            <pubDate>Fri, 16 Dec 2011 13:58:38 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=673</guid>
        </item>
        <item>
            <title>ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=672</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 672 - julius&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...&lt;/div&gt;~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v&lt;br /&gt;~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Mon, 12 Dec 2011 22:32:30 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=672</guid>
        </item>
        <item>
            <title>ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=671</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 671 - julius&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ...&lt;/div&gt;~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S&lt;br /&gt;~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Mon, 12 Dec 2011 22:14:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=671</guid>
        </item>
        <item>
            <title>Changing bugurl as we have bugzilla now</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=670</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 670 - olof&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Changing bugurl as we have bugzilla now&lt;/div&gt;~ /openrisc/trunk/gnu-src/bld-all.sh&lt;br /&gt;</description>
            <author>olof</author>
            <pubDate>Mon, 12 Dec 2011 18:34:43 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=670</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 source cleanup, delete uncecessary code</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=669</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 669 - filepang&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 source cleanup, delete uncecessary code&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Fri, 09 Dec 2011 14:01:25 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=669</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 add missing 'make clean' in make script</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=668</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 668 - filepang&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 add missing 'make clean' in make script&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/Makefile&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Thu, 08 Dec 2011 23:04:13 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=668</guid>
        </item>
        <item>
            <title>Corrected ITLB/DTLB values according to the arch spec.
This partially fixes ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=667</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 667 - olof&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Corrected ITLB/DTLB values according to the arch spec.&lt;br /&gt;
This partially fixes ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/include/spr-defs.h&lt;br /&gt;</description>
            <author>olof</author>
            <pubDate>Wed, 07 Dec 2011 17:47:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=667</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 minimal set of standard demo task is working</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=666</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 666 - filepang&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 minimal set of standard demo task is working&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/FreeRTOSConfig.h&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/sim.cfg&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Tue, 06 Dec 2011 14:41:40 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=666</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 fix context save/restore stack size bug
 remove unnecessary line</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=665</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 665 - filepang&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 fix context save/restore stack size bug&lt;br /&gt;
 remove unnecessary line&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portmacro.h&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Tue, 06 Dec 2011 14:34:29 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=665</guid>
        </item>
        <item>
            <title>FreeRTOSV6.1.1
 modify processor abstraction layer.
 now,all tasks are running in ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=664</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 664 - filepang&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;FreeRTOSV6.1.1&lt;br /&gt;
 modify processor abstraction layer.&lt;br /&gt;
 now,all tasks are running in ...&lt;/div&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S&lt;br /&gt;~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portmacro.h&lt;br /&gt;</description>
            <author>filepang</author>
            <pubDate>Tue, 06 Dec 2011 14:27:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=664</guid>
        </item>
        <item>
            <title>Fix compatibility problems with GCC 4.6.1. Fix a bug with ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=663</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 663 - jeremybennett&lt;/strong&gt; (21 file(s) modified)&lt;/div&gt;&lt;div&gt;Fix compatibility problems with GCC 4.6.1. Fix a bug with ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/bfd/ChangeLog.or32&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/bfd/elf-bfd.h&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/bfd/elf-eh-frame.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/bfd/elf.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/bfd/verilog.c&lt;br /&gt;+ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/ChangeLog.or32&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/dwarf.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/ieee.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/objdump.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/rddbg.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/readelf.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/binutils/stabs.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/as.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/ChangeLog.or32&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/listing.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/read.c&lt;br /&gt;+ /openrisc/trunk/gnu-src/binutils-2.20.1/ld/ChangeLog.or32&lt;br /&gt;~ /openrisc/trunk/gnu-src/binutils-2.20.1/ld/ldlang.c&lt;br /&gt;~ /openrisc/trunk/gnu-src/boards/or32-elf-sim.exp&lt;br /&gt;~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32&lt;br /&gt;~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.md&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Fri, 02 Dec 2011 19:17:14 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2F&amp;rev=663</guid>
        </item>
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