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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2F& Sun, 15 Mar 2026 21:01:37 +0100 FeedCreator 1.7.2 ORPSoC: Commit for bug 85 - add DSX support to ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=807 <div><strong>Rev 807 - julius</strong> (6 file(s) modified)</div><div>ORPSoC: Commit for bug 85 - add DSX support to ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsx.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsxinsn.S<br /> julius Sat, 26 May 2012 23:26:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=807 OR1200: Fix for bug 90 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=806 <div><strong>Rev 806 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 90<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br /> julius Sat, 26 May 2012 23:10:57 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=806 ORPSoC: Fix for bug 90 - EPCR on range exception ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=805 <div><strong>Rev 805 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 90 - EPCR on range exception ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-range.S<br /> julius Sat, 26 May 2012 23:09:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=805 OR1200: Fix for bug 91 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=804 <div><strong>Rev 804 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 91<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br /> julius Sat, 26 May 2012 22:57:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=804 ORPSoC: Fix for bug 91, l.sub not setting overflow flag ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=803 <div><strong>Rev 803 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 91, l.sub not setting overflow flag ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ov.S<br /> julius Sat, 26 May 2012 22:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=803 OR1200: Fix for bug 88 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=802 <div><strong>Rev 802 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 88<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br /> julius Mon, 21 May 2012 17:48:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=802 ORPSoC: Fix bug 88 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=801 <div><strong>Rev 801 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix bug 88<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88</a></div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ext.S<br /> julius Mon, 21 May 2012 17:41:34 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=801 FreeRTOSV6.1.1 add or32_dma demo task for test dcache manuplation function ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=800 <div><strong>Rev 800 - filepang</strong> (12 file(s) modified)</div><div>FreeRTOSV6.1.1<br /> add or32_dma demo task for test dcache manuplation function ...</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/board.h<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/dma<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/dma/or32_dma.c<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/dma/or32_dma.h<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/dma.c<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/dma.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/FreeRTOSConfig.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/Makefile.inc<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/sim.cfg<br /> filepang Wed, 09 May 2012 02:44:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=800 FreeRTOSV6.1.1 add cache related function from u-boot from OpenRISC ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=799 <div><strong>Rev 799 - filepang</strong> (8 file(s) modified)</div><div>FreeRTOSV6.1.1<br /> add cache related function from u-boot from OpenRISC<br /> ...</div>+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/cache.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/interrupts.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/reset.S<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/spr_defs.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/support.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port_spr_defs.h<br /> filepang Tue, 08 May 2012 02:05:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=799 Added drivers for ethmac and sdcard_mass_storage_controller https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=798 <div><strong>Rev 798 - skrzyp</strong> (17 file(s) modified)</div><div>Added drivers for ethmac and sdcard_mass_storage_controller</div>+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current/cdl<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current/cdl/devs_disk_opencores_sdcmsc.cdl<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current/ChangeLog<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current/src<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/disk/opencores/sdcmsc/current/src/if_sdcmsc.c<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/cdl<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/cdl/opencores_ethmac_eth_drivers.cdl<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/ChangeLog<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/src<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/devs/eth/opencores/ethmac/current/src/if_ethmac.c<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/ecos.db<br /> skrzyp Sat, 05 May 2012 16:59:02 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=798 testsuite: kill test processes that timeout https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=797 <div><strong>Rev 797 - pgavin</strong> (8 file(s) modified)</div><div>testsuite: kill test processes that timeout</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/lib/libsim.exp<br />~ /openrisc/trunk/or1ksim/testsuite/lib/or1ksim.exp<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br /> pgavin Fri, 27 Apr 2012 12:10:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=797 Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly. https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=796 <div><strong>Rev 796 - yannv</strong> (1 file(s) modified)</div><div>Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly.</div>~ /openrisc/trunk/bootloaders/orpmon/cmds/eth.c<br /> yannv Tue, 24 Apr 2012 09:23:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=796 Created or1200_rel3 branch from rev 794 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=795 <div><strong>Rev 795 - olof</strong> (1 file(s) modified)</div><div>Created or1200_rel3 branch from rev 794</div>+ /openrisc/branches/or1200_rel3<br /> olof Mon, 23 Apr 2012 18:26:50 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=795 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file Fixes lint ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=794 <div><strong>Rev 794 - julius</strong> (4 file(s) modified)</div><div>ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file<br /> <br /> Fixes lint ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv_except.v<br /> julius Wed, 18 Apr 2012 08:17:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=794 Corrected Julius Baxter's email address in MAINTAINERS https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=793 <div><strong>Rev 793 - jeremybennett</strong> (1 file(s) modified)</div><div>Corrected Julius Baxter's email address in MAINTAINERS</div>~ /openrisc/trunk/or1ksim/MAINTAINERS<br /> jeremybennett Sat, 07 Apr 2012 09:17:35 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=793 Added a MAINTAINERS file. 012-04-07 Jeremy Bennett <jeremy.bennett@embecosm. ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=792 <div><strong>Rev 792 - jeremybennett</strong> (7 file(s) modified)</div><div>Added a MAINTAINERS file.<br /> <br /> 012-04-07 Jeremy Bennett <<a href="mailto:jeremy.bennett@embecosm.com">jeremy.bennett@embecosm.com</a>><br /> <br /> * MAINTAINERS: ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />+ /openrisc/trunk/or1ksim/MAINTAINERS<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br /> jeremybennett Sat, 07 Apr 2012 09:15:10 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=792 Added options to configure RAM and ROM sizes. Fixed cache ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=791 <div><strong>Rev 791 - skrzyp</strong> (9 file(s) modified)</div><div>Added options to configure RAM and ROM sizes. Fixed cache ...</div>~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/include/hal_cache.h<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/vectors.S<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/cdl/hal_openrisc_orpsoc.cdl<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/include/pkgconf/mlt_openrisc_orpsoc_ram.h<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/include/pkgconf/mlt_openrisc_orpsoc_ram.ldi<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/include/pkgconf/mlt_openrisc_orpsoc_rom.h<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/include/pkgconf/mlt_openrisc_orpsoc_rom.ldi<br />+ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/include/plf_cache.h<br /> skrzyp Wed, 04 Apr 2012 14:49:45 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=791 fixed issues with context switching, interrupts, optimizations and cleanups https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=790 <div><strong>Rev 790 - skrzyp</strong> (6 file(s) modified)</div><div>fixed issues with context switching, interrupts, optimizations and cleanups</div>~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/cdl/hal_openrisc.cdl<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/include/basetype.h<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/include/hal_arch.h<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/context.S<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/hal_misc.c<br />~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/arch/current/src/vectors.S<br /> skrzyp Wed, 28 Mar 2012 14:29:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=790 ORPSoC: Patch from R Diez to make RTL sim report ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=789 <div><strong>Rev 789 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: Patch from R Diez to make RTL sim report ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br /> julius Sat, 24 Mar 2012 18:52:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=789 or1200: Patch from R Diez to remove l.cust5 signal from ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=788 <div><strong>Rev 788 - julius</strong> (2 file(s) modified)</div><div>or1200: Patch from R Diez to remove l.cust5 signal from ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br /> julius Sat, 24 Mar 2012 18:13:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2F&rev=788

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