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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F& Wed, 17 Jun 2026 22:38:48 +0100 FeedCreator 1.7.2 Big OR1200 update - FPU, data cache write-back added, spec ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=258 <div><strong>Rev 258 - julius</strong> (73 file(s) modified)</div><div>Big OR1200 update - FPU, data cache write-back added, spec ...</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />+ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_ram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_tag.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram_256x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_addsub.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_arith.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_div.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_fcmp.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_mul.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_div.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_mul.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_if.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_iwb_biu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_pic.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_pm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_qmem_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rf.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sb.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sb_fifo.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_32x24.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_32_bw.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x14.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x22.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_64x24.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_128x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_256x21.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_512x20.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x8.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_1024x32_bw.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x8.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_tpram_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v<br /> julius Mon, 30 Aug 2010 23:32:25 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=258 Changed or1200 supplementary manual from referring or or1200v2 to be ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=257 <div><strong>Rev 257 - julius</strong> (4 file(s) modified)</div><div>Changed or1200 supplementary manual from referring or or1200v2 to be ...</div>- /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt<br />- /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.pdf<br />+ /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt<br />+ /openrisc/trunk/docs/openrisc1200_supplementary_prm.pdf<br /> julius Mon, 30 Aug 2010 13:12:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=257 Linux patch update - disabled SCET driver by default https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=256 <div><strong>Rev 256 - julius</strong> (1 file(s) modified)</div><div>Linux patch update - disabled SCET driver by default</div>~ /openrisc/trunk/linux/patches/linux-2.6.34-or32.patch.bz2<br /> julius Sun, 29 Aug 2010 18:18:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=256 Linux patch update with USB host data cache issue solved, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=255 <div><strong>Rev 255 - julius</strong> (1 file(s) modified)</div><div>Linux patch update with USB host data cache issue solved, ...</div>~ /openrisc/trunk/linux/patches/linux-2.6.34-or32.patch.bz2<br /> julius Fri, 27 Aug 2010 16:19:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=255 Update of Linux patch with USB driver, rename of its ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=254 <div><strong>Rev 254 - julius</strong> (1 file(s) modified)</div><div>Update of Linux patch with USB driver, rename of its ...</div>~ /openrisc/trunk/linux/patches/linux-2.6.34-or32.patch.bz2<br /> julius Thu, 26 Aug 2010 23:22:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=254 No need to define PROTOTYPES, now DWARF 2 debugging is ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=253 <div><strong>Rev 253 - jeremybennett</strong> (1 file(s) modified)</div><div>No need to define PROTOTYPES, now DWARF 2 debugging is ...</div>~ /openrisc/trunk/gnu-src/boards/or32-sim.exp<br /> jeremybennett Thu, 26 Aug 2010 12:31:55 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=253 Changes to use source and line info when DWARF debug ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=252 <div><strong>Rev 252 - jeremybennett</strong> (3 file(s) modified)</div><div>Changes to use source and line info when DWARF debug ...</div>~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/or32-tdep.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/testsuite/ChangeLog.or32<br /> jeremybennett Thu, 26 Aug 2010 12:28:45 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=252 Bug in register enum declaration fixed in or32. Bug with ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=251 <div><strong>Rev 251 - jeremybennett</strong> (3 file(s) modified)</div><div>Bug in register enum declaration fixed in or32. Bug with ...</div>~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/or32.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/vec.h<br /> jeremybennett Thu, 26 Aug 2010 12:28:07 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=251 Specify -DPROTOTYPES to work round problems with K&amp;R style declarations ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=250 <div><strong>Rev 250 - jeremybennett</strong> (1 file(s) modified)</div><div>Specify -DPROTOTYPES to work round problems with K&amp;R style declarations ...</div>~ /openrisc/trunk/gnu-src/boards/or32-sim.exp<br /> jeremybennett Wed, 25 Aug 2010 08:02:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=250 Corrected handling of double args to dummy calls. Better way ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=249 <div><strong>Rev 249 - jeremybennett</strong> (1 file(s) modified)</div><div>Corrected handling of double args to dummy calls. Better way ...</div>~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/or32-tdep.c<br /> jeremybennett Wed, 25 Aug 2010 08:01:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=249 Fixed two bugs in GDB tests. * gdb.base/break.exp: Test for breakpoint ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=248 <div><strong>Rev 248 - jeremybennett</strong> (3 file(s) modified)</div><div>Fixed two bugs in GDB tests.<br /> <br /> * gdb.base/break.exp: Test for breakpoint ...</div>+ /openrisc/trunk/gnu-src/gdb-7.1/gdb/testsuite/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/testsuite/gdb.base/break.exp<br />~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/testsuite/gdb.base/call-sc.exp<br /> jeremybennett Wed, 25 Aug 2010 07:59:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=248 Set DWARF2 as the default debugging format. Clear out redundant ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=247 <div><strong>Rev 247 - jeremybennett</strong> (4 file(s) modified)</div><div>Set DWARF2 as the default debugging format. Clear out redundant ...</div>~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/elf.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/or32.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/or32.md<br /> jeremybennett Wed, 25 Aug 2010 07:57:43 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=247 ORPmon update - compatiable with new GCC, added new spr-defs ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=246 <div><strong>Rev 246 - julius</strong> (26 file(s) modified)</div><div>ORPmon update - compatiable with new GCC, added new spr-defs ...</div>~ /openrisc/trunk/bootloaders/orpmon/cmds/camera.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/cpu.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/dhry.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/eth.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/load.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/memory.c<br />~ /openrisc/trunk/bootloaders/orpmon/common/common.c<br />~ /openrisc/trunk/bootloaders/orpmon/common/spincursor.c<br />~ /openrisc/trunk/bootloaders/orpmon/common/support.c<br />~ /openrisc/trunk/bootloaders/orpmon/config.mk<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/eth.c<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/int.c<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/tick.c<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/uart.c<br />~ /openrisc/trunk/bootloaders/orpmon/flash.ld<br />~ /openrisc/trunk/bootloaders/orpmon/include/board.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/spincursor.h<br />+ /openrisc/trunk/bootloaders/orpmon/include/spr-defs.h<br />- /openrisc/trunk/bootloaders/orpmon/include/spr_defs.h<br />~ /openrisc/trunk/bootloaders/orpmon/ram.ld<br />~ /openrisc/trunk/bootloaders/orpmon/reset.S<br />~ /openrisc/trunk/bootloaders/orpmon/services/modem.c<br />~ /openrisc/trunk/bootloaders/orpmon/services/net.c<br />~ /openrisc/trunk/bootloaders/orpmon/services/tftp.c<br />~ /openrisc/trunk/bootloaders/orpmon/sim.cfg<br /> julius Mon, 23 Aug 2010 18:06:57 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=246 Fixed minor glitch in build script. Corrected newlib options and ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=245 <div><strong>Rev 245 - jeremybennett</strong> (3 file(s) modified)</div><div>Fixed minor glitch in build script. Corrected newlib options and ...</div>~ /openrisc/trunk/gnu-src/bld.sh<br />~ /openrisc/trunk/gnu-src/boards/or32-sim.exp<br />~ /openrisc/trunk/gnu-src/README<br /> jeremybennett Fri, 20 Aug 2010 10:28:26 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=245 Don't try to skip prologue using SAL info (fails with ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=244 <div><strong>Rev 244 - jeremybennett</strong> (4 file(s) modified)</div><div>Don't try to skip prologue using SAL info (fails with ...</div>~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gdb-7.1/gdb/or32-tdep.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/ChangeLog<br />~ /openrisc/trunk/gnu-src/gdb-7.1/sim/or32/wrapper.c<br /> jeremybennett Fri, 20 Aug 2010 10:27:26 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=244 Fixed libgloss for compiled code with leading underscores removed. * libgloss/or32/crt0.S ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=243 <div><strong>Rev 243 - jeremybennett</strong> (3 file(s) modified)</div><div>Fixed libgloss for compiled code with leading underscores removed.<br /> <br /> * libgloss/or32/crt0.S ...</div>~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/ChangeLog<br />+ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/crt0.S<br /> jeremybennett Fri, 20 Aug 2010 10:24:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=243 Generate global symbols without leading underscore. Tidy up generation of ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=242 <div><strong>Rev 242 - jeremybennett</strong> (6 file(s) modified)</div><div>Generate global symbols without leading underscore. Tidy up generation of ...</div>~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/ChangeLog<br />+ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/elf.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/linux-elf.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/or32.h<br />~ /openrisc/trunk/gnu-src/gcc-4.2.2/gcc/config/or32/or32.S<br /> jeremybennett Fri, 20 Aug 2010 10:23:00 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=242 Ensure register and symbol operands are never confused. * gas/config/tc-or32. ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=241 <div><strong>Rev 241 - jeremybennett</strong> (2 file(s) modified)</div><div>Ensure register and symbol operands are never confused.<br /> <br /> * gas/config/tc-or32.c (parse_operand): ...</div>+ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/binutils-2.20.1/gas/config/tc-or32.c<br /> jeremybennett Fri, 20 Aug 2010 10:20:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=241 or1ksim build fixups for Cygwin copilation https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=240 <div><strong>Rev 240 - julius</strong> (7 file(s) modified)</div><div>or1ksim build fixups for Cygwin copilation</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/or32/generate.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/or32.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/eth.h<br />~ /openrisc/trunk/or1ksim/sim-cmd.c<br /> julius Sun, 08 Aug 2010 09:22:56 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=240 or1ksim fixed SPR_VR_RESV value https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=239 <div><strong>Rev 239 - julius</strong> (2 file(s) modified)</div><div>or1ksim fixed SPR_VR_RESV value</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br /> julius Fri, 06 Aug 2010 13:13:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=239
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