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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&
Thu, 11 Jun 2026 13:59:33 +0100
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Adding gcc-4.5.1 patches to enable kernel to build again
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=378
<div><strong>Rev 378 - julius</strong> (100 file(s) modified)</div><div>Adding gcc-4.5.1 patches to enable kernel to build again</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/caller-save.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/combine.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/alpha/alpha.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/i386/i386.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/i386/i386.md<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/pa/pa.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/rs6000/x-aix<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/rx/predicates.md<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/rx/rx.md<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/sparc/sparc.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/spu/spu.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/convert.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/cp/decl.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/cp/init.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/emit-rtl.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/expmed.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fold-const.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/cpp.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/cpp.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/gfortran.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/gfortran.texi<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/gfortranspec.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/intrinsic.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/intrinsic.texi<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/invoke.texi<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/lang-specs.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/lang.opt<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/match.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/module.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/parse.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/scanner.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/symbol.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/trans-decl.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/fortran/trans.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/function.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/haifa-sched.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ifcvt.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ipa-prop.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ipa-pure-const.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/optabs.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/postreload.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/reginfo.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/rtl.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/rtlanal.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/sched-deps.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/cast.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/iop.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/named_refs.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv1p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv2p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv3p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv4p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv5p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv6p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv7p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/rv8p.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/cpp0x/unnamed_refs.C<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/init/value8.C<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/other/i386-8.C<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/pr45112.C<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.dg/tree-ssa/pr44914.C<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.c-torture/compile/pr45109.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.c-torture/execute/pr44858.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.c-torture/execute/pr45034.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.c-torture/execute/pr45262.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20030107-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20030702-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20050309-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20050325-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20050330-2.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/20051201-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/gomp/pr27573.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/gomp/pr34610.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/graphite/interchange-0.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/lto/20090313_0.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/lto/20091216-1_0.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/march.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/mtune.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/pr24225.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/pr26570.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/pr32773.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/pr45055.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/pr45259.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/profile-dir-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/profile-dir-2.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/profile-dir-3.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/tree-ssa/sra-10.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/i386/pr45296.c<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gfortran.dg/allocate_derived_3.f90<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gfortran.dg/gomp/pr27573.f90<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gfortran.dg/gomp/pr44036-1.f90<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/lib/gcc-dg.exp<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-flow.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-sra.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-ssa-loop-ivopts.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-ssa-loop-prefetch.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-ssa-structalias.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/tree-vect-patterns.c<br />
julius
Thu, 30 Sep 2010 11:30:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=378
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gcc-4.5.1/gcc/config/or32/or32.c:
Swap INTVAL for REGNO in or32_legitimate_address_p fixing ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=377
<div><strong>Rev 377 - julius</strong> (1 file(s) modified)</div><div>gcc-4.5.1/gcc/config/or32/or32.c:<br />
Swap INTVAL for REGNO in or32_legitimate_address_p fixing 64-bit<br />
machine build errors.</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.c<br />
julius
Wed, 29 Sep 2010 20:01:05 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=377
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Adding handling cases for RSP queries seen from new gdb-7.2 ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=376
<div><strong>Rev 376 - julius</strong> (5 file(s) modified)</div><div>Adding handling cases for RSP queries seen from new gdb-7.2 ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/debug/rsp-server.c<br />+ /openrisc/trunk/or_debug_proxy/ChangeLog<br />~ /openrisc/trunk/or_debug_proxy/src/gdb.c<br />~ /openrisc/trunk/or_debug_proxy/src/or_debug_proxy.c<br />
julius
Sat, 25 Sep 2010 08:49:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=376
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ORPmon update for compatibility with OR toolchain 1.0rc1
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=375
<div><strong>Rev 375 - julius</strong> (6 file(s) modified)</div><div>ORPmon update for compatibility with OR toolchain 1.0rc1</div>~ /openrisc/trunk/bootloaders/orpmon/common/common.c<br />~ /openrisc/trunk/bootloaders/orpmon/config.mk<br />~ /openrisc/trunk/bootloaders/orpmon/include/board.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />~ /openrisc/trunk/bootloaders/orpmon/ram.ld<br />~ /openrisc/trunk/bootloaders/orpmon/reset.S<br />
julius
Fri, 24 Sep 2010 15:22:13 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=375
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ORPSoCv2 adding some files forgotten from last checkin
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=374
<div><strong>Rev 374 - julius</strong> (3 file(s) modified)</div><div>ORPSoCv2 adding some files forgotten from last checkin</div>+ /openrisc/trunk/orpsocv2/sw/include/simple-spi.h<br />+ /openrisc/trunk/orpsocv2/sw/or1200/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/support/simple-spi.c<br />
julius
Fri, 24 Sep 2010 15:20:49 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=374
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ORPSoCv2 software update for compatibility with OR toolchain 1.0
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=373
<div><strong>Rev 373 - julius</strong> (8 file(s) modified)</div><div>ORPSoCv2 software update for compatibility with OR toolchain 1.0</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v<br />~ /openrisc/trunk/orpsocv2/sw/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-except.S<br />~ /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S<br />~ /openrisc/trunk/orpsocv2/sw/support/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/or1200-mmu.S<br />
julius
Fri, 24 Sep 2010 15:19:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=373
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Toolchain install script uClibc variable update
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=372
<div><strong>Rev 372 - julius</strong> (1 file(s) modified)</div><div>Toolchain install script uClibc variable update</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 12:17:39 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=372
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Toolchain install script binutils commented out fix
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=371
<div><strong>Rev 371 - julius</strong> (1 file(s) modified)</div><div>Toolchain install script binutils commented out fix</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 12:05:37 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=371
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Toolchain install script uclibc url fix
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=370
<div><strong>Rev 370 - julius</strong> (1 file(s) modified)</div><div>Toolchain install script uclibc url fix</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 12:03:03 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=370
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Toolchain build script binutils path fix
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=369
<div><strong>Rev 369 - julius</strong> (1 file(s) modified)</div><div>Toolchain build script binutils path fix</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 11:18:05 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=369
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Toolchain script: adding sim url path
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=368
<div><strong>Rev 368 - julius</strong> (1 file(s) modified)</div><div>Toolchain script: adding sim url path</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 11:09:21 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=368
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Fixup 1.0 release script
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=367
<div><strong>Rev 367 - julius</strong> (1 file(s) modified)</div><div>Fixup 1.0 release script</div>~ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 11:04:37 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=367
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Version 1.0 toolchain script commit
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=366
<div><strong>Rev 366 - julius</strong> (1 file(s) modified)</div><div>Version 1.0 toolchain script commit</div>+ /openrisc/trunk/toolchain_install_scripts/crossbuild-1.0.sh<br />
julius
Fri, 24 Sep 2010 10:54:42 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=366
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Linux-2.6.34 patch update with updated USB ohs900 host
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=365
<div><strong>Rev 365 - julius</strong> (1 file(s) modified)</div><div>Linux-2.6.34 patch update with updated USB ohs900 host</div>~ /openrisc/trunk/linux/patches/linux-2.6.34-or32.patch.bz2<br />
julius
Tue, 21 Sep 2010 16:46:55 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=365
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OR1200 passes verilator lint. Mainly fixes to widths, and all ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=364
<div><strong>Rev 364 - julius</strong> (41 file(s) modified)</div><div>OR1200 passes verilator lint. Mainly fixes to widths, and all ...</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dmmu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_arith.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_fcmp.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_addsub.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_div.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_intfloat_conv.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_post_norm_mul.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_addsub.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_pre_norm_div.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_lsu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_operandmuxes.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_reg2mem.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_arith.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_fcmp.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_div.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_intfloat_conv.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_defines.v<br />
julius
Sun, 12 Sep 2010 17:48:45 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=364
-
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=363
<div><strong>Rev 363 - julius</strong> (38 file(s) modified)</div><div>ORPSoC's RTL code fixed to pass linting by Verilator.<br />
<br />
ORPSoC's debug ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />
julius
Sun, 12 Sep 2010 07:57:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=363
-
ORPSoCv2 verilator building working again. Board build fixes to follow
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=362
<div><strong>Rev 362 - julius</strong> (7 file(s) modified)</div><div>ORPSoCv2 verilator building working again. Board build fixes to follow</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 10 Sep 2010 22:42:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=362
-
OPRSoCv2 - adding things left out in last check-in
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=361
<div><strong>Rev 361 - julius</strong> (36 file(s) modified)</div><div>OPRSoCv2 - adding things left out in last check-in</div>+ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/uart_stim.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/rom<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/rom/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/rom/rom.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/fifo4.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/simple_spi.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/README<br />+ /openrisc/trunk/orpsocv2/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S<br />+ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/include/board.h<br />- /openrisc/trunk/orpsocv2/sw/include/eth-phy-mii.h<br />- /openrisc/trunk/orpsocv2/sw/include/open-eth.h<br />- /openrisc/trunk/orpsocv2/sw/include/or1200-defines.h<br />- /openrisc/trunk/orpsocv2/sw/include/sdram.h<br />- /openrisc/trunk/orpsocv2/sw/include/simple-spi.h<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S<br />~ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />- /openrisc/trunk/orpsocv2/sw/support/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/utils/bin2vlogarray.c<br />
julius
Fri, 10 Sep 2010 18:09:37 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=361
-
First checkin of new ORPSoC set up - more to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=360
<div><strong>Rev 360 - julius</strong> (94 file(s) modified)</div><div>First checkin of new ORPSoC set up - more to ...</div>- /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines_old.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_register.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth<br />- /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_startup<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_top<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/spi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/raminfr.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart16550.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_sdram_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_switch_b3<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/out<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Fri, 10 Sep 2010 17:51:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=360
-
Removing duplicate OR1200 spec from docs/ path, original in or1200/doc ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=359
<div><strong>Rev 359 - julius</strong> (6 file(s) modified)</div><div>Removing duplicate OR1200 spec from docs/ path, original in or1200/doc ...</div>- /openrisc/trunk/docs/openrisc1200_spec.doc<br />- /openrisc/trunk/docs/openrisc1200_spec.pdf<br />- /openrisc/trunk/docs/openrisc1200_spec_0.7_jp.doc<br />- /openrisc/trunk/docs/openrisc1200_spec_0.7_jp.pdf<br />+ /openrisc/trunk/or1200/doc/openrisc1200_spec_0.7_jp.doc<br />+ /openrisc/trunk/or1200/doc/openrisc1200_spec_0.7_jp.pdf<br />
julius
Fri, 10 Sep 2010 11:18:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=359
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