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openrisc
WebSVN RSS feed - openrisc
https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&
Sun, 15 Mar 2026 20:54:14 +0100
FeedCreator 1.7.2
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ORPSoC ml501 updates - increased frequency, updated documentation
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=496
<div><strong>Rev 496 - julius</strong> (6 file(s) modified)</div><div>ORPSoC ml501 updates - increased frequency, updated documentation</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/uart_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />
julius
Mon, 07 Mar 2011 11:52:26 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=496
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ORPSoC adding more accessor functions to Micron SDRAM model.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=495
<div><strong>Rev 495 - julius</strong> (1 file(s) modified)</div><div>ORPSoC adding more accessor functions to Micron SDRAM model.</div>~ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v<br />
julius
Mon, 07 Mar 2011 11:44:55 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=495
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Change to ensure handles ctrl-C correctly with empty line.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=494
<div><strong>Rev 494 - jeremybennett</strong> (8 file(s) modified)</div><div>Change to ensure handles ctrl-C correctly with empty line.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/sim-cmd.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Thu, 24 Feb 2011 18:07:27 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=494
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ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=493
<div><strong>Rev 493 - julius</strong> (1 file(s) modified)</div><div>ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues.</div>~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/Makefile<br />
julius
Tue, 22 Feb 2011 09:48:23 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=493
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ORPSoC VPI interface for modelsim and documentation update
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=492
<div><strong>Rev 492 - julius</strong> (3 file(s) modified)</div><div>ORPSoC VPI interface for modelsim and documentation update</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />
julius
Mon, 21 Feb 2011 11:45:17 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=492
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ORPSoC or1200_monitor update.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=491
<div><strong>Rev 491 - julius</strong> (1 file(s) modified)</div><div>ORPSoC or1200_monitor update.</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />
julius
Mon, 21 Feb 2011 00:56:47 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=491
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Updates to fix spurious test failures and register scheduling.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=490
<div><strong>Rev 490 - jeremybennett</strong> (19 file(s) modified)</div><div>Updates to fix spurious test failures and register scheduling.</div>~ /openrisc/trunk/gnu-src/bld-all.sh<br />~ /openrisc/trunk/gnu-src/bld-bb.sh<br />~ /openrisc/trunk/gnu-src/boards/or32-linux-sim.exp<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config.gcc<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.md<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/uclibc-stdint.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/c99-init-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/c99-stdint-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/c99-stdint-2.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/c99-stdint-7.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/glibc-uclibc-1.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/glibc-uclibc-2.c<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/lib/target-supports.exp<br />+ /openrisc/trunk/gnu-src/gcc-4.5.1/libstdc++-v3/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/libstdc++-v3/testsuite/18_support/numeric_limits/lowest.cc<br />~ /openrisc/trunk/gnu-src/site.exp<br />
jeremybennett
Wed, 16 Feb 2011 19:11:45 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=490
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ORPSoC sw cleanup. Remove warnings.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=489
<div><strong>Rev 489 - julius</strong> (7 file(s) modified)</div><div>ORPSoC sw cleanup. Remove warnings.</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/lib-utils.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c<br />
julius
Fri, 11 Feb 2011 12:33:23 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=489
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ORPSoC OR1200 driver - tick timer exception handler reverted to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=488
<div><strong>Rev 488 - julius</strong> (4 file(s) modified)</div><div>ORPSoC OR1200 driver - tick timer exception handler reverted to ...</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c<br />
julius
Fri, 11 Feb 2011 11:56:04 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=488
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ORPSoC main software makefile update
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=487
<div><strong>Rev 487 - julius</strong> (1 file(s) modified)</div><div>ORPSoC main software makefile update</div>~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Tue, 08 Feb 2011 14:10:30 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=487
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ORPSoC updates, mainly software, i2c driver
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=486
<div><strong>Rev 486 - julius</strong> (6 file(s) modified)</div><div>ORPSoC updates, mainly software, i2c driver</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Tue, 08 Feb 2011 14:06:45 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=486
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ORPSoC updates - or1200 monitor now has separate defines file, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=485
<div><strong>Rev 485 - julius</strong> (33 file(s) modified)</div><div>ORPSoC updates - or1200 monitor now has separate defines file, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/utils/marksec<br />- /openrisc/trunk/orpsocv2/sw/utils/merge2srec<br />
julius
Fri, 04 Feb 2011 09:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=485
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Changes to make r12 call-saved and to bring wchar tests ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=484
<div><strong>Rev 484 - jeremybennett</strong> (5 file(s) modified)</div><div>Changes to make r12 call-saved and to bring wchar tests ...</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/linux-elf.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.h<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/testsuite/gcc.dg/c99-init-1.c<br />
jeremybennett
Thu, 03 Feb 2011 11:20:47 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=484
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Updated with new opcodes to generate random numbers and to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=483
<div><strong>Rev 483 - jeremybennett</strong> (20 file(s) modified)</div><div>Updated with new opcodes to generate random numbers and to ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/libtoplevel.c<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/peripheral/memory.c<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h<br />~ /openrisc/trunk/or1ksim/toplevel-mprofile.c<br />~ /openrisc/trunk/or1ksim/toplevel-profile.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.h<br />~ /openrisc/trunk/or1ksim/toplevel.c<br />
jeremybennett
Tue, 01 Feb 2011 09:18:23 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=483
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Don't hardcode tool versions in help text
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=482
<div><strong>Rev 482 - olof</strong> (1 file(s) modified)</div><div>Don't hardcode tool versions in help text</div>~ /openrisc/trunk/gnu-src/bld-all.sh<br />
olof
Sun, 30 Jan 2011 21:13:30 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=482
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OR1200 Update. RTL and spec.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=481
<div><strong>Rev 481 - julius</strong> (23 file(s) modified)</div><div>OR1200 Update. RTL and spec.</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_ram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_tag.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_ram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_tag.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v<br />
julius
Wed, 19 Jan 2011 02:45:51 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=481
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ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=480
<div><strong>Rev 480 - julius</strong> (8 file(s) modified)</div><div>ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest<br />
julius
Tue, 18 Jan 2011 05:09:41 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=480
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ORPSoC update to ml501 board port. Memory controller caching fixed ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=479
<div><strong>Rev 479 - julius</strong> (11 file(s) modified)</div><div>ORPSoC update to ml501 board port. Memory controller caching fixed ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />
julius
Mon, 17 Jan 2011 05:44:06 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=479
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ORPSoC update - ml501 or1200 cache configuration set to maximum, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=478
<div><strong>Rev 478 - julius</strong> (4 file(s) modified)</div><div>ORPSoC update - ml501 or1200 cache configuration set to maximum, ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v<br />
julius
Sat, 15 Jan 2011 14:01:36 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=478
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ORPSoC update - Added ability to enable OR1200 caches up ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=477
<div><strong>Rev 477 - julius</strong> (13 file(s) modified)</div><div>ORPSoC update - Added ability to enable OR1200 caches up ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />
julius
Sat, 15 Jan 2011 05:48:25 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=477
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