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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&
Wed, 20 May 2026 03:33:32 +0100
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porting serial port management task, interrupt hander
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=636
<div><strong>Rev 636 - filepang</strong> (1 file(s) modified)</div><div>porting serial port management task, interrupt hander</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/serial/serial.c<br />
filepang
Fri, 26 Aug 2011 14:36:02 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=636
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Patch for http://bugzilla.opencores.org/show_bug.cgi?id=69.
* ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=635
<div><strong>Rev 635 - jeremybennett</strong> (2 file(s) modified)</div><div>Patch for <a href="http://bugzilla.opencores.org/show_bug.cgi?id=69" target="_blank">http://bugzilla.opencores.org/show_bug.cgi?id=69</a>.<br />
<br />
* ...</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/linux-elf.h<br />
jeremybennett
Thu, 25 Aug 2011 10:51:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=635
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orpsoc: atlys: autoregenerate coregen cores
Instead of keeping binary .ngc files ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=634
<div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br />
<br />
Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br />
stekern
Wed, 24 Aug 2011 03:28:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=634
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orpsoc: add Digilent Atlys spartan6 board README
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=633
<div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br />
stekern
Wed, 24 Aug 2011 03:28:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=633
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orpsoc: add Digilent Atlys spartan6 board sw include file
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=632
<div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br />
<br />
Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br />
stekern
Wed, 24 Aug 2011 03:28:27 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=632
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orpsoc: add Digilent Atlys spartan6 board testbench
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=631
<div><strong>Rev 631 - stekern</strong> (12 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board testbench<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v<br />
stekern
Wed, 24 Aug 2011 03:28:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=631
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orpsoc: add Digilent Atlys spartan6 board backend
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=630
<div><strong>Rev 630 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board backend<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf<br />
stekern
Wed, 24 Aug 2011 03:28:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=630
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orpsoc: add Digilent Atlys spartan6 board or1ksim configuration
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=629
<div><strong>Rev 629 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board or1ksim configuration<br />
<br />
Signed-off-by: Stefan Kristiansson ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg<br />
stekern
Wed, 24 Aug 2011 03:28:14 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=629
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orpsoc: add Digilent Atlys spartan6 board Makefiles
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=628
<div><strong>Rev 628 - stekern</strong> (22 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board Makefiles<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile<br />
stekern
Wed, 24 Aug 2011 03:28:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=628
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orpsoc: add Digilent Atlys spartan6 board rtl
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=627
<div><strong>Rev 627 - stekern</strong> (42 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board rtl<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v<br />
stekern
Wed, 24 Aug 2011 03:28:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=627
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Fix to support GCC 4.6 by disabling -Werror.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=626
<div><strong>Rev 626 - jeremybennett</strong> (1 file(s) modified)</div><div>Fix to support GCC 4.6 by disabling -Werror.</div>~ /openrisc/trunk/gnu-src/bld-all.sh<br />
jeremybennett
Mon, 15 Aug 2011 12:36:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=626
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Fixed configuration to work with GCC 4.6, added -Werror to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=625
<div><strong>Rev 625 - jeremybennett</strong> (83 file(s) modified)</div><div>Fixed configuration to work with GCC 4.6, added -Werror to ...</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/pcu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/pcu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
jeremybennett
Mon, 15 Aug 2011 11:44:46 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=625
-
add missing delay slot instruction
vPortDisableInterrupts
vPortEnableInterrupts
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=624
<div><strong>Rev 624 - filepang</strong> (1 file(s) modified)</div><div>add missing delay slot instruction<br />
vPortDisableInterrupts<br />
vPortEnableInterrupts</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S<br />
filepang
Sun, 14 Aug 2011 07:22:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=624
-
cleanup source code
Demo/OpenRISC_SIM_GCC/arch/support. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=623
<div><strong>Rev 623 - filepang</strong> (7 file(s) modified)</div><div>cleanup source code <br />
Demo/OpenRISC_SIM_GCC/arch/support.h<br />
Demo/OpenRISC_SIM_GCC/arch/interrupts.h<br />
Demo/OpenRISC_SIM_GCC/arch/link.ld<br />
<br />
add gpio driver<br />
<br />
add gpio base address definition</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/board.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/interrupts.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/link.ld<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/support.h<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/gpio.c<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/gpio.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/Makefile<br />
filepang
Sat, 13 Aug 2011 15:46:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=623
-
update uart driver for support multiple uart cores
...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=622
<div><strong>Rev 622 - filepang</strong> (3 file(s) modified)</div><div>update uart driver for support multiple uart cores <br />
...</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c<br />
filepang
Sat, 13 Aug 2011 13:39:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=622
-
update sim.cfg for newer version of Or1ksim.
remove unused files.
cleanup source ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=621
<div><strong>Rev 621 - filepang</strong> (17 file(s) modified)</div><div>update sim.cfg for newer version of Or1ksim.<br />
remove unused files.<br />
cleanup source ...</div>- /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/int.c<br />- /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/int.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/interrupts.c<br />+ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/interrupts.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/reset.S<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/support.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/Makefile<br />- /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/tick.c<br />- /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/tick.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/sim.cfg<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/port.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portasm.S<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Source/portable/GCC/OpenRISC/portmacro.h<br />
filepang
Thu, 11 Aug 2011 21:45:13 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=621
-
remove unused file
cleanup makefile
update uart_init(), disable interrupt before initialize.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=620
<div><strong>Rev 620 - jeremybennett</strong> (6 file(s) modified)</div><div>remove unused file<br />
cleanup makefile<br />
update uart_init(), disable interrupt before initialize.</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/tick.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/tick.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/Makefile<br />
jeremybennett
Thu, 11 Aug 2011 08:45:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=620
-
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=619
<div><strong>Rev 619 - julius</strong> (2 file(s) modified)</div><div>ORPSoC OR1200 fix and regression test for bug 51.<br />
<br />
signed-off Julius ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br />
julius
Tue, 02 Aug 2011 21:06:40 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=619
-
Remove unused parameter Tp
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=618
<div><strong>Rev 618 - olof</strong> (16 file(s) modified)</div><div>Remove unused parameter Tp</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br />
olof
Tue, 02 Aug 2011 13:52:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=618
-
Set tx_negedge correctly (Fixes bug #12)
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=617
<div><strong>Rev 617 - olof</strong> (1 file(s) modified)</div><div>Set tx_negedge correctly (Fixes bug #12)</div>~ /openrisc/trunk/or1k_startup/rtl/verilog/spi_top.v<br />
olof
Fri, 29 Jul 2011 10:48:05 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=617
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