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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&
Thu, 18 Jun 2026 05:42:45 +0100
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ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=65
<div><strong>Rev 65 - julius</strong> (2 file(s) modified)</div><div>ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix</div>~ /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />
julius
Sat, 23 Jan 2010 04:46:00 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=65
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Trying to fix the system c model jtagsc.h checkout problem, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=64
<div><strong>Rev 64 - julius</strong> (10 file(s) modified)</div><div>Trying to fix the system c model jtagsc.h checkout problem, ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />- /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Wed, 20 Jan 2010 09:36:54 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=64
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Finally adding RSP server to cycle accurate model, based on ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=63
<div><strong>Rev 63 - julius</strong> (49 file(s) modified)</div><div>Finally adding RSP server to cycle accurate model, based on ...</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp<br />~ /openrisc/trunk/orpsocv2/sw/utils/Makefile<br />
julius
Sun, 10 Jan 2010 12:31:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=63
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This material is part of the separate website downloads directory.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=62
<div><strong>Rev 62 - jeremybennett</strong> (1 file(s) modified)</div><div>This material is part of the separate website downloads directory.</div>- /openrisc/trunk/or1ksim/downloads<br />
jeremybennett
Wed, 30 Dec 2009 09:17:05 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=62
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The build directory should not be part of the SVN ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=61
<div><strong>Rev 61 - jeremybennett</strong> (1 file(s) modified)</div><div>The build directory should not be part of the SVN ...</div>- /openrisc/trunk/or1ksim/build<br />
jeremybennett
Wed, 30 Dec 2009 08:59:04 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=61
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Mark Jarvin's patches to support Mac OS X (Snow Leopard).
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=60
<div><strong>Rev 60 - jeremybennett</strong> (13 file(s) modified)</div><div>Mark Jarvin's patches to support Mac OS X (Snow Leopard).</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.1<br />~ /openrisc/trunk/or1ksim/autom4te.cache/requests<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.1<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/config.h.in<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/peripheral/atadevice.c<br />~ /openrisc/trunk/or1ksim/port/strndup.c<br />~ /openrisc/trunk/or1ksim/sim-cmd.c<br />
jeremybennett
Wed, 23 Dec 2009 15:47:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=60
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Toolchain install script gcc patch change and gdb configure change
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=59
<div><strong>Rev 59 - julius</strong> (1 file(s) modified)</div><div>Toolchain install script gcc patch change and gdb configure change</div>~ /openrisc/trunk/toolchain_install_scripts/MOF_ORSOC_TCHN_v5c_or32-elf.sh<br />
julius
Wed, 02 Dec 2009 15:26:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=59
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ORPSoC2 update - added fpu and implemented in processor, also ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=58
<div><strong>Rev 58 - julius</strong> (49 file(s) modified)</div><div>ORPSoC2 update - added fpu and implemented in processor, also ...</div>+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/add_sub27.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/div_r2.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/except.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fcmp.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/mul_r2.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm_fmul.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_fpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_wbmux.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/basic/basic.S<br />~ /openrisc/trunk/orpsocv2/sw/cbasic/cbasic.c<br />~ /openrisc/trunk/orpsocv2/sw/cust/cust.c<br />~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/eth/eth-basic.c<br />~ /openrisc/trunk/orpsocv2/sw/eth/eth-int.c<br />~ /openrisc/trunk/orpsocv2/sw/eth/except.S<br />~ /openrisc/trunk/orpsocv2/sw/except/except_test.c<br />+ /openrisc/trunk/orpsocv2/sw/fpu<br />+ /openrisc/trunk/orpsocv2/sw/fpu/fpu.S<br />+ /openrisc/trunk/orpsocv2/sw/fpu/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/icm/icm.S<br />~ /openrisc/trunk/orpsocv2/sw/mul/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/mul/mul.c<br />~ /openrisc/trunk/orpsocv2/sw/support/except.S<br />+ /openrisc/trunk/orpsocv2/sw/support/fp.c<br />~ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/spr_defs.h<br />~ /openrisc/trunk/orpsocv2/sw/support/support.c<br />~ /openrisc/trunk/orpsocv2/sw/support/support.h<br />+ /openrisc/trunk/orpsocv2/sw/support/syscall.c<br />~ /openrisc/trunk/orpsocv2/sw/uart/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/uart/uart.c<br />
julius
Sun, 29 Nov 2009 16:46:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=58
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ORPSoC execution logs created by event sim and cycle accurate ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=57
<div><strong>Rev 57 - julius</strong> (4 file(s) modified)</div><div>ORPSoC execution logs created by event sim and cycle accurate ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Tue, 24 Nov 2009 12:48:15 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=57
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adding generic pll model to orpsoc
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=56
<div><strong>Rev 56 - julius</strong> (1 file(s) modified)</div><div>adding generic pll model to orpsoc</div>+ /openrisc/trunk/orpsocv2/backend/generic_pll.v<br />
julius
Mon, 16 Nov 2009 10:36:54 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=56
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Added modelsim support to makefile. Moved buffer libraries to sensible ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=55
<div><strong>Rev 55 - julius</strong> (41 file(s) modified)</div><div>Added modelsim support to makefile. Moved buffer libraries to sensible ...</div>- /openrisc/trunk/orpsocv2/backend/gbuf.v<br />+ /openrisc/trunk/orpsocv2/backend/generic_buffers.v<br />+ /openrisc/trunk/orpsocv2/backend/generic_gbuf.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/copyright.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_buffers.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_gbuf.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_sync.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/tmp.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_16_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />
julius
Fri, 13 Nov 2009 20:25:39 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=55
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wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=54
<div><strong>Rev 54 - julius</strong> (8 file(s) modified)</div><div>wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist</div>+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_arb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/intercon.vm<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />
julius
Tue, 03 Nov 2009 13:17:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=54
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Fixed incorrect commandline option for ORPSoC and main makefile setting
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=53
<div><strong>Rev 53 - julius</strong> (2 file(s) modified)</div><div>Fixed incorrect commandline option for ORPSoC and main makefile setting</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 16 Oct 2009 12:34:44 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=53
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ORPSoC update - ability to dump part or all of ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=52
<div><strong>Rev 52 - julius</strong> (5 file(s) modified)</div><div>ORPSoC update - ability to dump part or all of ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />
julius
Thu, 15 Oct 2009 16:31:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=52
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ORPSoCv2 updates: cycle accurate profiling, ELF loading
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=51
<div><strong>Rev 51 - julius</strong> (17 file(s) modified)</div><div>ORPSoCv2 updates: cycle accurate profiling, ELF loading</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/except.S<br />~ /openrisc/trunk/orpsocv2/sw/support/time.c<br />
julius
Thu, 01 Oct 2009 14:17:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=51
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Adding or32_funcs.S
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=50
<div><strong>Rev 50 - julius</strong> (1 file(s) modified)</div><div>Adding or32_funcs.S</div>+ /openrisc/trunk/orpsocv2/sw/support/or32_funcs.S<br />
julius
Thu, 01 Oct 2009 10:09:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=50
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Lots of ORPSoC Updates. Cycle accurate model update. Enabled block ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=49
<div><strong>Rev 49 - julius</strong> (39 file(s) modified)</div><div>Lots of ORPSoC Updates. Cycle accurate model update. Enabled block ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cfgr.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/except.S<br />~ /openrisc/trunk/orpsocv2/sw/support/int.c<br />~ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/orp.ld<br />~ /openrisc/trunk/orpsocv2/sw/support/support.c<br />~ /openrisc/trunk/orpsocv2/sw/support/support.h<br />+ /openrisc/trunk/orpsocv2/sw/support/time.c<br />+ /openrisc/trunk/orpsocv2/sw/support/time.h<br />
julius
Sat, 12 Sep 2009 20:25:34 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=49
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Adds an initialization to keep GCC happy in jp1_ll_read_jp1.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=48
<div><strong>Rev 48 - jeremybennett</strong> (1 file(s) modified)</div><div>Adds an initialization to keep GCC happy in jp1_ll_read_jp1.</div>~ /openrisc/trunk/gdb/gdb-6.8/gdb/or1k-jtag.c<br />
jeremybennett
Sat, 12 Sep 2009 17:26:09 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=48
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debug proxy speed increase, block transfers possible with cpu aslong ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=47
<div><strong>Rev 47 - julius</strong> (10 file(s) modified)</div><div>debug proxy speed increase, block transfers possible with cpu aslong ...</div>~ /openrisc/trunk/or_debug_proxy/includes/or_debug_proxy.h<br />~ /openrisc/trunk/or_debug_proxy/includes/usb_driver_calls.h<br />~ /openrisc/trunk/or_debug_proxy/includes/usb_functions.h<br />~ /openrisc/trunk/or_debug_proxy/Makefile<br />~ /openrisc/trunk/or_debug_proxy/README<br />~ /openrisc/trunk/or_debug_proxy/src/gdb.c<br />~ /openrisc/trunk/or_debug_proxy/src/linux_usb_driver_calls.c<br />~ /openrisc/trunk/or_debug_proxy/src/or_debug_proxy.c<br />~ /openrisc/trunk/or_debug_proxy/src/usb_functions.c<br />~ /openrisc/trunk/or_debug_proxy/src/win_usb_driver_calls.c<br />
julius
Thu, 03 Sep 2009 09:44:30 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=47
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debug interfaces now support byte and non-aligned accesses from gdb
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=46
<div><strong>Rev 46 - julius</strong> (16 file(s) modified)</div><div>debug interfaces now support byte and non-aligned accesses from gdb</div>~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v<br />~ /openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c<br />~ /openrisc/trunk/or_debug_proxy/includes/or_debug_proxy.h<br />~ /openrisc/trunk/or_debug_proxy/includes/usb_functions.h<br />~ /openrisc/trunk/or_debug_proxy/Makefile<br />~ /openrisc/trunk/or_debug_proxy/README<br />~ /openrisc/trunk/or_debug_proxy/src/gdb.c<br />~ /openrisc/trunk/or_debug_proxy/src/or_debug_proxy.c<br />~ /openrisc/trunk/or_debug_proxy/src/usb_functions.c<br />
julius
Fri, 28 Aug 2009 09:07:56 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2F&rev=46
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