OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Error creating feed file, please check write permissions.
openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F& Sat, 18 Apr 2026 06:50:54 +0100 FeedCreator 1.7.2 Declare pcreg_boot before usage When things were moved around in rev ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=852 <div><strong>Rev 852 - olof</strong> (1 file(s) modified)</div><div>Declare pcreg_boot before usage<br /> <br /> When things were moved around in rev ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br /> olof Thu, 08 Nov 2012 19:08:55 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=852 or1200_genpc: fix ipcu_cycstb_o generation In some circumstances the CPU is still ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=847 <div><strong>Rev 847 - stekern</strong> (2 file(s) modified)</div><div>or1200_genpc: fix ipcu_cycstb_o generation<br /> <br /> In some circumstances the CPU is still ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br /> stekern Thu, 25 Oct 2012 03:29:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=847 or1200: Fix for cache bug related to first_{hit|miss}_ack Under certain circumstances, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=846 <div><strong>Rev 846 - stekern</strong> (2 file(s) modified)</div><div>or1200: Fix for cache bug related to first_{hit|miss}_ack<br /> <br /> Under certain circumstances, ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v<br /> stekern Thu, 25 Oct 2012 03:28:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=846 or1200: l.lws support Using the l.lws instruction doesn't work currently. It simply ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=845 <div><strong>Rev 845 - stekern</strong> (2 file(s) modified)</div><div>or1200: l.lws support<br /> <br /> Using the l.lws instruction doesn't work currently.<br /> It simply ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br /> stekern Thu, 25 Oct 2012 03:28:56 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=845 OR1200 debug unit: prevent deadlock when trap instruction stalls As per ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=815 <div><strong>Rev 815 - yannv</strong> (2 file(s) modified)</div><div>OR1200 debug unit: prevent deadlock when trap instruction stalls<br /> <br /> As per ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br /> yannv Thu, 04 Oct 2012 09:52:36 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=815 or1200: Set correct PC after reset when parameter boot_adr is ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=813 <div><strong>Rev 813 - olof</strong> (4 file(s) modified)</div><div>or1200: Set correct PC after reset when parameter boot_adr is ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br /> olof Wed, 19 Sep 2012 17:03:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=813 OR1200: Regenerate documentation. Forgot newline in version history table, so last ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=809 <div><strong>Rev 809 - julius</strong> (2 file(s) modified)</div><div>OR1200: Regenerate documentation.<br /> <br /> Forgot newline in version history table, so last ...</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br /> julius Sat, 26 May 2012 23:35:20 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=809 OR1200: Add DSX bit support to SR. Updated documentation, revision is ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=808 <div><strong>Rev 808 - julius</strong> (6 file(s) modified)</div><div>OR1200: Add DSX bit support to SR.<br /> <br /> Updated documentation, revision is ...</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br /> julius Sat, 26 May 2012 23:31:57 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=808 OR1200: Fix for bug 90 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=806 <div><strong>Rev 806 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 90<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br /> julius Sat, 26 May 2012 23:10:57 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=806 OR1200: Fix for bug 91 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=804 <div><strong>Rev 804 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 91<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br /> julius Sat, 26 May 2012 22:57:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=804 OR1200: Fix for bug 88 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=802 <div><strong>Rev 802 - julius</strong> (1 file(s) modified)</div><div>OR1200: Fix for bug 88<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88</a></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br /> julius Mon, 21 May 2012 17:48:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=802 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file Fixes lint ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=794 <div><strong>Rev 794 - julius</strong> (4 file(s) modified)</div><div>ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file<br /> <br /> Fixes lint ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv_except.v<br /> julius Wed, 18 Apr 2012 08:17:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=794 or1200: Patch from R Diez to remove l.cust5 signal from ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=788 <div><strong>Rev 788 - julius</strong> (2 file(s) modified)</div><div>or1200: Patch from R Diez to remove l.cust5 signal from ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br /> julius Sat, 24 Mar 2012 18:13:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=788 Allow setting the boot address as an external parameter. If no ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=679 <div><strong>Rev 679 - olof</strong> (4 file(s) modified)</div><div>Allow setting the boot address as an external<br /> parameter. If no ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br /> olof Wed, 29 Feb 2012 18:04:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=679 or1200: Fix for Bug 76 - Incorrect unsigned integer less-than ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=674 <div><strong>Rev 674 - julius</strong> (1 file(s) modified)</div><div>or1200: Fix for Bug 76 - Incorrect unsigned integer less-than ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br /> julius Wed, 18 Jan 2012 09:34:35 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=674 or1200: update documentation to go with recent rtl commits https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=647 <div><strong>Rev 647 - julius</strong> (2 file(s) modified)</div><div>or1200: update documentation to go with recent rtl commits</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br /> julius Mon, 19 Sep 2011 19:16:43 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=647 or1200: Specification document source now in asciidoc format. ODT and ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=645 <div><strong>Rev 645 - julius</strong> (30 file(s) modified)</div><div>or1200: Specification document source now in asciidoc format. ODT and ...</div>+ /openrisc/trunk/or1200/doc/docbook-xsl.css<br />+ /openrisc/trunk/or1200/doc/docbook.xsl<br />+ /openrisc/trunk/or1200/doc/gen-docinfo.pl<br />+ /openrisc/trunk/or1200/doc/img<br />+ /openrisc/trunk/or1200/doc/img/addr_translation.gif<br />+ /openrisc/trunk/or1200/doc/img/core_arch.gif<br />+ /openrisc/trunk/or1200/doc/img/core_interfaces.gif<br />+ /openrisc/trunk/or1200/doc/img/cpu_fpu_dsp.gif<br />+ /openrisc/trunk/or1200/doc/img/data_cache_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/debug_unit_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/dev_interface_cycles.gif<br />+ /openrisc/trunk/or1200/doc/img/inst_cache_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/inst_mmu_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/interrupt_controller.gif<br />+ /openrisc/trunk/or1200/doc/img/or_family.gif<br />+ /openrisc/trunk/or1200/doc/img/powerup_seq.gif<br />+ /openrisc/trunk/or1200/doc/img/powerup_seq_gatedclk.gif<br />+ /openrisc/trunk/or1200/doc/img/tlb_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/watchpoint_trigger.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_block_read.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_compatible.png<br />+ /openrisc/trunk/or1200/doc/img/wb_read.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_rw.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_write.gif<br />+ /openrisc/trunk/or1200/doc/Makefile<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />+ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br />+ /openrisc/trunk/or1200/doc/preprocess.pl<br /> julius Thu, 01 Sep 2011 19:55:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=645 or1200: the infamous l.rfe fix, and bug fix for when ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=644 <div><strong>Rev 644 - julius</strong> (2 file(s) modified)</div><div>or1200: the infamous l.rfe fix, and bug fix for when ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:56:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=644 or1200: new ALU comparision implementation option, TLB invalidate register indicated ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=643 <div><strong>Rev 643 - julius</strong> (4 file(s) modified)</div><div>or1200: new ALU comparision implementation option, TLB invalidate register indicated ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rf.v<br /> julius Thu, 01 Sep 2011 18:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=643 or1200: add carry, overflow bits, and range exception https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=642 <div><strong>Rev 642 - julius</strong> (6 file(s) modified)</div><div>or1200: add carry, overflow bits, and range exception</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br /> julius Thu, 01 Sep 2011 18:49:24 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2F&rev=642

Browse

Tools