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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F& Sun, 15 Mar 2026 19:55:16 +0100 FeedCreator 1.7.2 Adding single precision FPU to or1200, initial checkin, not fully ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=185 <div><strong>Rev 185 - julius</strong> (15 file(s) modified)</div><div>Adding single precision FPU to or1200, initial checkin, not fully ...</div>~ /openrisc/trunk/bootloaders/orpmon/include/board.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_amultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cfgr.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wbmux.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/Makefile<br /> julius Sun, 11 Jul 2010 15:28:17 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=185 Changed conditionals for Verilator to &quot;verilator&quot; instead of ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=111 <div><strong>Rev 111 - jeremybennett</strong> (1 file(s) modified)</div><div>Changed conditionals for Verilator to &quot;verilator&quot; instead of &quot;VERILATOR&quot;.</div>~ /openrisc/trunk/orpsocv2/backend/generic_pll.v<br /> jeremybennett Wed, 09 Jun 2010 13:41:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=111 Fixed typo in Silos workaround script https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=78 <div><strong>Rev 78 - rherveille</strong> (1 file(s) modified)</div><div>Fixed typo in Silos workaround script</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> rherveille Wed, 07 Apr 2010 18:32:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=78 Added support for Silvaco's Silos simulator Added workaround for Silos's exit ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=77 <div><strong>Rev 77 - rherveille</strong> (1 file(s) modified)</div><div>Added support for Silvaco's Silos simulator<br /> Added workaround for Silos's exit ...</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> rherveille Wed, 07 Apr 2010 18:15:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=77 Added: +libext+.v Added: +incdir+. https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=76 <div><strong>Rev 76 - rherveille</strong> (1 file(s) modified)</div><div>Added: +libext+.v<br /> Added: +incdir+.</div>~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br /> rherveille Tue, 06 Apr 2010 18:43:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=76 ORPSoC board builds, adding readmes https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=71 <div><strong>Rev 71 - julius</strong> (3 file(s) modified)</div><div>ORPSoC board builds, adding readmes</div>+ /openrisc/trunk/orpsocv2/boards/readme.txt<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/readme.txt<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br /> julius Tue, 23 Feb 2010 09:02:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=71 ORPSoC cycle accurate trace generation now compatible with latest version ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=70 <div><strong>Rev 70 - julius</strong> (3 file(s) modified)</div><div>ORPSoC cycle accurate trace generation now compatible with latest version ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br /> julius Fri, 19 Feb 2010 04:22:14 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=70 ORPSoC xilinx ml501 board update - added ethernet eupport and ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=69 <div><strong>Rev 69 - julius</strong> (31 file(s) modified)</div><div>ORPSoC xilinx ml501 board update - added ethernet eupport and ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.ld<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth_reset.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/except.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/mii.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/open_eth.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/filer<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/TODO<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Fri, 19 Feb 2010 03:25:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=69 Fixed up a couple of Makefile things in ORPSoCv2 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=68 <div><strong>Rev 68 - julius</strong> (2 file(s) modified)</div><div>Fixed up a couple of Makefile things in ORPSoCv2</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br /> julius Tue, 16 Feb 2010 11:47:17 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=68 New synthesizable builds of ORPSoC - first for the Xilinx ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=67 <div><strong>Rev 67 - julius</strong> (107 file(s) modified)</div><div>New synthesizable builds of ORPSoC - first for the Xilinx ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards<br />+ /openrisc/trunk/orpsocv2/boards/tools.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ddr2_model_parameters.vh<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_chipscope.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_ctrl.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_idelay_ctrl.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mem_if_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mig.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_calib.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_ctl_io.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dm_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dqs_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dq_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_init.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_io.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_write.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_addr_fifo.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_rd.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_wr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/dummy_slave.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_params.vh<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v.prev<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if_cache.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/reset_debounce.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ssram_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/usr_rst.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_conbus_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_lfsr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/modelsim.scr<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.ld<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot_reset.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.ld<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio_reset.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.ld<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest_reset.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501.xcf<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_ddr2_wb_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_xst.tpl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/timescale.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_clgen.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_shift.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_clgen.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_shift.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/support/reset.S<br />~ /openrisc/trunk/orpsocv2/sw/support/uart.c<br />~ /openrisc/trunk/orpsocv2/sw/support/uart.h<br />~ /openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c<br /> julius Tue, 16 Feb 2010 08:58:52 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=67 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=66 <div><strong>Rev 66 - julius</strong> (8 file(s) modified)</div><div>Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/support.c<br /> julius Wed, 27 Jan 2010 10:49:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=66 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=65 <div><strong>Rev 65 - julius</strong> (2 file(s) modified)</div><div>ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix</div>~ /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br /> julius Sat, 23 Jan 2010 04:46:00 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=65 Trying to fix the system c model jtagsc.h checkout problem, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=64 <div><strong>Rev 64 - julius</strong> (10 file(s) modified)</div><div>Trying to fix the system c model jtagsc.h checkout problem, ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />- /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Wed, 20 Jan 2010 09:36:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=64 Finally adding RSP server to cycle accurate model, based on ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=63 <div><strong>Rev 63 - julius</strong> (49 file(s) modified)</div><div>Finally adding RSP server to cycle accurate model, based on ...</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp<br />~ /openrisc/trunk/orpsocv2/sw/utils/Makefile<br /> julius Sun, 10 Jan 2010 12:31:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=63 ORPSoC2 update - added fpu and implemented in processor, also ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=58 <div><strong>Rev 58 - julius</strong> (49 file(s) modified)</div><div>ORPSoC2 update - added fpu and implemented in processor, also ...</div>+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/add_sub27.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/div_r2.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/except.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fcmp.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/mul_r2.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm_fmul.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_fpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_wbmux.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/basic/basic.S<br />~ /openrisc/trunk/orpsocv2/sw/cbasic/cbasic.c<br />~ /openrisc/trunk/orpsocv2/sw/cust/cust.c<br />~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/eth/eth-basic.c<br />~ /openrisc/trunk/orpsocv2/sw/eth/eth-int.c<br />~ /openrisc/trunk/orpsocv2/sw/eth/except.S<br />~ /openrisc/trunk/orpsocv2/sw/except/except_test.c<br />+ /openrisc/trunk/orpsocv2/sw/fpu<br />+ /openrisc/trunk/orpsocv2/sw/fpu/fpu.S<br />+ /openrisc/trunk/orpsocv2/sw/fpu/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/icm/icm.S<br />~ /openrisc/trunk/orpsocv2/sw/mul/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/mul/mul.c<br />~ /openrisc/trunk/orpsocv2/sw/support/except.S<br />+ /openrisc/trunk/orpsocv2/sw/support/fp.c<br />~ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/spr_defs.h<br />~ /openrisc/trunk/orpsocv2/sw/support/support.c<br />~ /openrisc/trunk/orpsocv2/sw/support/support.h<br />+ /openrisc/trunk/orpsocv2/sw/support/syscall.c<br />~ /openrisc/trunk/orpsocv2/sw/uart/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/uart/uart.c<br /> julius Sun, 29 Nov 2009 16:46:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=58 ORPSoC execution logs created by event sim and cycle accurate ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=57 <div><strong>Rev 57 - julius</strong> (4 file(s) modified)</div><div>ORPSoC execution logs created by event sim and cycle accurate ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Tue, 24 Nov 2009 12:48:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=57 adding generic pll model to orpsoc https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=56 <div><strong>Rev 56 - julius</strong> (1 file(s) modified)</div><div>adding generic pll model to orpsoc</div>+ /openrisc/trunk/orpsocv2/backend/generic_pll.v<br /> julius Mon, 16 Nov 2009 10:36:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=56 Added modelsim support to makefile. Moved buffer libraries to sensible ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=55 <div><strong>Rev 55 - julius</strong> (41 file(s) modified)</div><div>Added modelsim support to makefile. Moved buffer libraries to sensible ...</div>- /openrisc/trunk/orpsocv2/backend/gbuf.v<br />+ /openrisc/trunk/orpsocv2/backend/generic_buffers.v<br />+ /openrisc/trunk/orpsocv2/backend/generic_gbuf.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/copyright.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_buffers.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_gbuf.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_sync.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/tmp.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_16_ip.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br /> julius Fri, 13 Nov 2009 20:25:39 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=55 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=54 <div><strong>Rev 54 - julius</strong> (8 file(s) modified)</div><div>wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist</div>+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_arb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/intercon.vm<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br /> julius Tue, 03 Nov 2009 13:17:50 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=54 Fixed incorrect commandline option for ORPSoC and main makefile setting https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=53 <div><strong>Rev 53 - julius</strong> (2 file(s) modified)</div><div>Fixed incorrect commandline option for ORPSoC and main makefile setting</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Fri, 16 Oct 2009 12:34:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=53
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