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openrisc
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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&
Sun, 15 Mar 2026 19:42:44 +0100
FeedCreator 1.7.2
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ORPSoC sw cleanup. Remove warnings.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=489
<div><strong>Rev 489 - julius</strong> (7 file(s) modified)</div><div>ORPSoC sw cleanup. Remove warnings.</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/lib-utils.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c<br />
julius
Fri, 11 Feb 2011 12:33:23 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=489
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ORPSoC OR1200 driver - tick timer exception handler reverted to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=488
<div><strong>Rev 488 - julius</strong> (4 file(s) modified)</div><div>ORPSoC OR1200 driver - tick timer exception handler reverted to ...</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-timerdemo.c<br />
julius
Fri, 11 Feb 2011 11:56:04 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=488
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ORPSoC main software makefile update
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=487
<div><strong>Rev 487 - julius</strong> (1 file(s) modified)</div><div>ORPSoC main software makefile update</div>~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Tue, 08 Feb 2011 14:10:30 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=487
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ORPSoC updates, mainly software, i2c driver
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=486
<div><strong>Rev 486 - julius</strong> (6 file(s) modified)</div><div>ORPSoC updates, mainly software, i2c driver</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Tue, 08 Feb 2011 14:06:45 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=486
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ORPSoC updates - or1200 monitor now has separate defines file, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=485
<div><strong>Rev 485 - julius</strong> (33 file(s) modified)</div><div>ORPSoC updates - or1200 monitor now has separate defines file, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/utils/marksec<br />- /openrisc/trunk/orpsocv2/sw/utils/merge2srec<br />
julius
Fri, 04 Feb 2011 09:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=485
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ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=480
<div><strong>Rev 480 - julius</strong> (8 file(s) modified)</div><div>ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest<br />
julius
Tue, 18 Jan 2011 05:09:41 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=480
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ORPSoC update to ml501 board port. Memory controller caching fixed ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=479
<div><strong>Rev 479 - julius</strong> (11 file(s) modified)</div><div>ORPSoC update to ml501 board port. Memory controller caching fixed ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />
julius
Mon, 17 Jan 2011 05:44:06 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=479
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ORPSoC update - ml501 or1200 cache configuration set to maximum, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=478
<div><strong>Rev 478 - julius</strong> (4 file(s) modified)</div><div>ORPSoC update - ml501 or1200 cache configuration set to maximum, ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v<br />
julius
Sat, 15 Jan 2011 14:01:36 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=478
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ORPSoC update - Added ability to enable OR1200 caches up ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=477
<div><strong>Rev 477 - julius</strong> (13 file(s) modified)</div><div>ORPSoC update - Added ability to enable OR1200 caches up ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />
julius
Sat, 15 Jan 2011 05:48:25 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=477
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ORPSoC updates. Added 16kB cache options to OR1200, now as ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=476
<div><strong>Rev 476 - julius</strong> (6 file(s) modified)</div><div>ORPSoC updates. Added 16kB cache options to OR1200, now as ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 14 Jan 2011 12:42:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=476
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ORPSoC main simulation makefile tidy up, addition of BSS test ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=475
<div><strong>Rev 475 - julius</strong> (8 file(s) modified)</div><div>ORPSoC main simulation makefile tidy up, addition of BSS test ...</div>+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/ordb1a3pe1500-or1ksim.cfg<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/ml501-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />+ /openrisc/trunk/orpsocv2/sim/bin/refdesign-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />
julius
Fri, 14 Jan 2011 10:09:21 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=475
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ORPSoC OR1200 crt0 updates.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=470
<div><strong>Rev 470 - julius</strong> (1 file(s) modified)</div><div>ORPSoC OR1200 crt0 updates.</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />
julius
Mon, 10 Jan 2011 10:05:26 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=470
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ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=468
<div><strong>Rev 468 - julius</strong> (14 file(s) modified)</div><div>ORPSoC update:<br />
Added USER_ELF and USER_VMEM options to reference design simulation ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Sun, 09 Jan 2011 08:57:32 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=468
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ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=466
<div><strong>Rev 466 - julius</strong> (2 file(s) modified)</div><div>ORPSoC updates: <br />
Add new test to determine processor's capabilities.<br />
Fix up ...</div>~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/README<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-configdetect.c<br />
julius
Sat, 08 Jan 2011 05:43:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=466
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ORPSoC SPI flash load Makefile and README updates.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=465
<div><strong>Rev 465 - julius</strong> (2 file(s) modified)</div><div>ORPSoC SPI flash load Makefile and README updates.</div>~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/README<br />
julius
Fri, 07 Jan 2011 15:28:06 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=465
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ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=462
<div><strong>Rev 462 - julius</strong> (53 file(s) modified)</div><div>ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.<br />
<br />
RAM ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />
julius
Fri, 07 Jan 2011 06:51:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=462
-
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=456
<div><strong>Rev 456 - julius</strong> (2 file(s) modified)</div><div>ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />
julius
Sun, 26 Dec 2010 14:14:57 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=456
-
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=449
<div><strong>Rev 449 - julius</strong> (12 file(s) modified)</div><div>ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.<br />
<br />
Replace use ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/README<br />
julius
Mon, 13 Dec 2010 19:01:07 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=449
-
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=439
<div><strong>Rev 439 - julius</strong> (45 file(s) modified)</div><div>ORPSoC update<br />
<br />
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A<br />
Ethernet MAC ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mul.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c<br />
julius
Mon, 06 Dec 2010 15:22:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=439
-
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=435
<div><strong>Rev 435 - julius</strong> (15 file(s) modified)</div><div>ORPSoC updates<br />
OR1200 multiply/MAC/division unit update with serial multiply and <br />
divide ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mul.c<br />
julius
Tue, 30 Nov 2010 00:08:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=435
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