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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F& Fri, 08 May 2026 11:13:08 +0100 FeedCreator 1.7.2 orpsoc: atlys: autoregenerate coregen cores Instead of keeping binary .ngc files ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=634 <div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br /> <br /> Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br /> stekern Wed, 24 Aug 2011 03:28:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=634 orpsoc: add Digilent Atlys spartan6 board README Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=633 <div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br /> <br /> Signed-off-by: Stefan Kristiansson &lt;<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>&gt;</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br /> stekern Wed, 24 Aug 2011 03:28:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=633 orpsoc: add Digilent Atlys spartan6 board sw include file Signed-off-by: Stefan ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=632 <div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br /> <br /> Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br /> stekern Wed, 24 Aug 2011 03:28:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=632 orpsoc: add Digilent Atlys spartan6 board testbench Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=631 <div><strong>Rev 631 - stekern</strong> (12 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board testbench<br /> <br /> Signed-off-by: Stefan Kristiansson &lt;<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>&gt;</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v<br /> stekern Wed, 24 Aug 2011 03:28:24 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=631 orpsoc: add Digilent Atlys spartan6 board backend Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=630 <div><strong>Rev 630 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board backend<br /> <br /> Signed-off-by: Stefan Kristiansson &lt;<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>&gt;</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf<br /> stekern Wed, 24 Aug 2011 03:28:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=630 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration Signed-off-by: Stefan ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=629 <div><strong>Rev 629 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board or1ksim configuration<br /> <br /> Signed-off-by: Stefan Kristiansson ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg<br /> stekern Wed, 24 Aug 2011 03:28:14 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=629 orpsoc: add Digilent Atlys spartan6 board Makefiles Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=628 <div><strong>Rev 628 - stekern</strong> (22 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board Makefiles<br /> <br /> Signed-off-by: Stefan Kristiansson &lt;<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>&gt;</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile<br /> stekern Wed, 24 Aug 2011 03:28:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=628 orpsoc: add Digilent Atlys spartan6 board rtl Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=627 <div><strong>Rev 627 - stekern</strong> (42 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board rtl<br /> <br /> Signed-off-by: Stefan Kristiansson &lt;<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>&gt;</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v<br /> stekern Wed, 24 Aug 2011 03:28:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=627 ORPSoC OR1200 fix and regression test for bug 51. signed-off Julius ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=619 <div><strong>Rev 619 - julius</strong> (2 file(s) modified)</div><div>ORPSoC OR1200 fix and regression test for bug 51.<br /> <br /> signed-off Julius ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br /> julius Tue, 02 Aug 2011 21:06:40 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=619 Remove unused parameter Tp https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=618 <div><strong>Rev 618 - olof</strong> (16 file(s) modified)</div><div>Remove unused parameter Tp</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br /> olof Tue, 02 Aug 2011 13:52:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=618 Fix white space in ethmac headers https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=570 <div><strong>Rev 570 - olof</strong> (20 file(s) modified)</div><div>Fix white space in ethmac headers</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br /> olof Mon, 18 Jul 2011 18:14:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=570 OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=568 <div><strong>Rev 568 - julius</strong> (115 file(s) modified)</div><div>OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin/s3adsp_ddr2_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/s3adsp1800.ucf<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/prebuilt<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/orpsoc_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/modules<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/s3adsp_ddr2_parameters_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cache.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_ctl.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_clk_dcm.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_controller_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_write_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_dqs_delay.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_0_wr_en_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_1_wr_en_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_ram8d_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_rd_gray_cntr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dm_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dqs_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dq_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_tap_dly.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_top_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_wr_gray_cntr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/out<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-1.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-2.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/out<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br /> julius Sat, 02 Jul 2011 10:28:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=568 ORPSoC ethmac test and diagnosis software program updates. https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=567 <div><strong>Rev 567 - julius</strong> (1 file(s) modified)</div><div>ORPSoC ethmac test and diagnosis software program updates.</div>~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br /> julius Sat, 02 Jul 2011 07:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=567 Update docs for new modules sub directory https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=564 <div><strong>Rev 564 - olof</strong> (1 file(s) modified)</div><div>Update docs for new modules sub directory</div>~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br /> olof Sun, 19 Jun 2011 21:54:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=564 Search for external cores in &lt;board&gt;/modules path https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=563 <div><strong>Rev 563 - olof</strong> (4 file(s) modified)</div><div>Search for external cores in &lt;board&gt;/modules path</div>+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/modules<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/modules<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-paths.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc<br /> olof Sun, 19 Jun 2011 21:19:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=563 ORPSoC - board modelsim makefile tab/space fixup https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=562 <div><strong>Rev 562 - julius</strong> (1 file(s) modified)</div><div>ORPSoC - board modelsim makefile tab/space fixup</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br /> julius Sun, 12 Jun 2011 13:08:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=562 ORPSoC update - update make scripts, XILINX_PATH setup changes. Note - ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=560 <div><strong>Rev 560 - julius</strong> (4 file(s) modified)</div><div>ORPSoC update - update make scripts, XILINX_PATH setup changes.<br /> <br /> Note - ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br /> julius Sat, 11 Jun 2011 22:32:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=560 ORPSoC makefile script fragments update. https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=558 <div><strong>Rev 558 - julius</strong> (4 file(s) modified)</div><div>ORPSoC makefile script fragments update.</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-benchsrc.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-tops.inc<br /> julius Thu, 09 Jun 2011 09:26:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=558 ORPSoC dbg_if fix for slow Wishbone slaves https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=547 <div><strong>Rev 547 - julius</strong> (1 file(s) modified)</div><div>ORPSoC dbg_if fix for slow Wishbone slaves</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br /> julius Wed, 01 Jun 2011 11:30:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=547 ORPSoC update: Fix WB B3 bursting termination on error in ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=546 <div><strong>Rev 546 - julius</strong> (1 file(s) modified)</div><div>ORPSoC update: Fix WB B3 bursting termination on error in ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br /> julius Tue, 31 May 2011 18:48:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=546
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