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openrisc
WebSVN RSS feed - openrisc
https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&
Tue, 10 Mar 2026 02:52:34 +0100
FeedCreator 1.7.2
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Allow setting the boot address as an external
parameter. If no ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=679
<div><strong>Rev 679 - olof</strong> (4 file(s) modified)</div><div>Allow setting the boot address as an external<br />
parameter. If no ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />
olof
Wed, 29 Feb 2012 18:04:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=679
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atlys: add 2-clock synchronizer chain for ddr2_calib_done
The signal ddr2_calib_done signal ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=677
<div><strong>Rev 677 - stekern</strong> (1 file(s) modified)</div><div>atlys: add 2-clock synchronizer chain for ddr2_calib_done<br />
<br />
The signal ddr2_calib_done signal ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />
stekern
Tue, 21 Feb 2012 16:01:04 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=677
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Multiple 64-bit fixes (mostly sign and size of constants). Fix ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=673
<div><strong>Rev 673 - yannv</strong> (13 file(s) modified)</div><div>Multiple 64-bit fixes (mostly sign and size of constants). Fix ...</div>~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-opc.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/or32.c<br />~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-dis.c<br />~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-opc.c<br />
yannv
Fri, 16 Dec 2011 13:58:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=673
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ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=672
<div><strong>Rev 672 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br />
julius
Mon, 12 Dec 2011 22:32:30 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=672
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ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=671
<div><strong>Rev 671 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ...</div>~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />
julius
Mon, 12 Dec 2011 22:14:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=671
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minor corrections to clean simulation files
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=662
<div><strong>Rev 662 - paknick</strong> (1 file(s) modified)</div><div>minor corrections to clean simulation files</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-simclean.inc<br />
paknick
Wed, 16 Nov 2011 17:27:17 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=662
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added makefile for icarus simulation
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=661
<div><strong>Rev 661 - paknick</strong> (1 file(s) modified)</div><div>added makefile for icarus simulation</div>+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-icarus.inc<br />
paknick
Wed, 16 Nov 2011 17:15:57 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=661
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updated makefiles for simulation with altera ordb2a-ep4ce22
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=660
<div><strong>Rev 660 - paknick</strong> (1 file(s) modified)</div><div>updated makefiles for simulation with altera ordb2a-ep4ce22</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br />
paknick
Wed, 16 Nov 2011 14:47:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=660
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orpsoc: cfi_ctrl software driver fix to allow compilation when it's ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=656
<div><strong>Rev 656 - julius</strong> (1 file(s) modified)</div><div>orpsoc: cfi_ctrl software driver fix to allow compilation when it's ...</div>~ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c<br />
julius
Sat, 22 Oct 2011 20:39:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=656
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ORPSoC: add CFI flash controller to ml501, sw driver, tests, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=655
<div><strong>Rev 655 - julius</strong> (45 file(s) modified)</div><div>ORPSoC: add CFI flash controller to ml501, sw driver, tests, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_BankLib.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_CUIcommandData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_data.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_def.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_TimingData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_UserData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/x28fxxxp30.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-sim-definesgen.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-swrules.inc<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.c<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.ld<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include/cfi_ctrl.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/Makefile<br />
julius
Sat, 22 Oct 2011 20:32:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=655
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Fix make compile.tcl for actel backend
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=652
<div><strong>Rev 652 - yannv</strong> (1 file(s) modified)</div><div>Fix make compile.tcl for actel backend</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />
yannv
Fri, 14 Oct 2011 13:33:55 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=652
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ORPSoC: The ability to use a free/gimped version of Modelsim ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=651
<div><strong>Rev 651 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: The ability to use a free/gimped version of Modelsim ...</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br />
julius
Sun, 09 Oct 2011 18:19:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=651
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ORPSoC: documentation update to fix explanation of Xilinx environment setup, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=650
<div><strong>Rev 650 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: documentation update to fix explanation of Xilinx environment setup, ...</div>~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />
julius
Sat, 08 Oct 2011 20:55:45 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=650
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orpsoc: xilinx: use XILINX env variable
instead of rely on custom ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=638
<div><strong>Rev 638 - stekern</strong> (9 file(s) modified)</div><div>orpsoc: xilinx: use XILINX env variable<br />
<br />
instead of rely on custom ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br />
stekern
Mon, 29 Aug 2011 03:19:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=638
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orpsoc: atlys: autoregenerate coregen cores
Instead of keeping binary .ngc files ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=634
<div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br />
<br />
Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br />
stekern
Wed, 24 Aug 2011 03:28:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=634
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orpsoc: add Digilent Atlys spartan6 board README
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=633
<div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br />
stekern
Wed, 24 Aug 2011 03:28:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=633
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orpsoc: add Digilent Atlys spartan6 board sw include file
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=632
<div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br />
<br />
Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br />
stekern
Wed, 24 Aug 2011 03:28:27 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=632
-
orpsoc: add Digilent Atlys spartan6 board testbench
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=631
<div><strong>Rev 631 - stekern</strong> (12 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board testbench<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v<br />
stekern
Wed, 24 Aug 2011 03:28:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=631
-
orpsoc: add Digilent Atlys spartan6 board backend
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=630
<div><strong>Rev 630 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board backend<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf<br />
stekern
Wed, 24 Aug 2011 03:28:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=630
-
orpsoc: add Digilent Atlys spartan6 board or1ksim configuration
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=629
<div><strong>Rev 629 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board or1ksim configuration<br />
<br />
Signed-off-by: Stefan Kristiansson ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg<br />
stekern
Wed, 24 Aug 2011 03:28:14 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=629
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