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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F& Thu, 16 Apr 2026 10:58:26 +0100 FeedCreator 1.7.2 Add OR1200_OR32_LWS define to board specific or1200_defines.v https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=854 <div><strong>Rev 854 - stekern</strong> (4 file(s) modified)</div><div>Add OR1200_OR32_LWS define to board specific or1200_defines.v</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v<br /> stekern Tue, 04 Dec 2012 04:27:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=854 Declare pcreg_boot before usage When things were moved around in rev ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=853 <div><strong>Rev 853 - olof</strong> (1 file(s) modified)</div><div>Declare pcreg_boot before usage<br /> <br /> When things were moved around in rev ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> olof Thu, 08 Nov 2012 19:17:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=853 or1200_genpc: fix ipcu_cycstb_o generation In some circumstances the CPU is still ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=850 <div><strong>Rev 850 - stekern</strong> (2 file(s) modified)</div><div>or1200_genpc: fix ipcu_cycstb_o generation<br /> <br /> In some circumstances the CPU is still ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> stekern Thu, 25 Oct 2012 03:30:22 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=850 or1200: Fix for cache bug related to first_{hit|miss}_ack Under certain circumstances, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=849 <div><strong>Rev 849 - stekern</strong> (2 file(s) modified)</div><div>or1200: Fix for cache bug related to first_{hit|miss}_ack<br /> <br /> Under certain circumstances, ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br /> stekern Thu, 25 Oct 2012 03:30:20 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=849 or1200: l.lws support Using the l.lws instruction doesn't work currently. It simply ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=848 <div><strong>Rev 848 - stekern</strong> (2 file(s) modified)</div><div>or1200: l.lws support<br /> <br /> Using the l.lws instruction doesn't work currently.<br /> It simply ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br /> stekern Thu, 25 Oct 2012 03:30:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=848 OR1200 debug unit: prevent deadlock when trap instruction stalls As per ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=815 <div><strong>Rev 815 - yannv</strong> (2 file(s) modified)</div><div>OR1200 debug unit: prevent deadlock when trap instruction stalls<br /> <br /> As per ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br /> yannv Thu, 04 Oct 2012 09:52:36 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=815 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=814 <div><strong>Rev 814 - olof</strong> (3 file(s) modified)</div><div>orpsoc/or1200: Set correct PC after reset when parameter boot_adr is ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br /> olof Wed, 19 Sep 2012 17:06:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=814 ORPSoC: Commit for bug 85 - add DSX support to ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=807 <div><strong>Rev 807 - julius</strong> (6 file(s) modified)</div><div>ORPSoC: Commit for bug 85 - add DSX support to ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsx.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsxinsn.S<br /> julius Sat, 26 May 2012 23:26:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=807 ORPSoC: Fix for bug 90 - EPCR on range exception ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=805 <div><strong>Rev 805 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 90 - EPCR on range exception ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-range.S<br /> julius Sat, 26 May 2012 23:09:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=805 ORPSoC: Fix for bug 91, l.sub not setting overflow flag ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=803 <div><strong>Rev 803 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 91, l.sub not setting overflow flag ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ov.S<br /> julius Sat, 26 May 2012 22:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=803 ORPSoC: Fix bug 88 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=801 <div><strong>Rev 801 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix bug 88<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88</a></div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ext.S<br /> julius Mon, 21 May 2012 17:41:34 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=801 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file Fixes lint ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=794 <div><strong>Rev 794 - julius</strong> (4 file(s) modified)</div><div>ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file<br /> <br /> Fixes lint ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv_except.v<br /> julius Wed, 18 Apr 2012 08:17:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=794 ORPSoC: Patch from R Diez to make RTL sim report ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=789 <div><strong>Rev 789 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: Patch from R Diez to make RTL sim report ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br /> julius Sat, 24 Mar 2012 18:52:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=789 or1200: Patch from R Diez to remove l.cust5 signal from ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=788 <div><strong>Rev 788 - julius</strong> (2 file(s) modified)</div><div>or1200: Patch from R Diez to remove l.cust5 signal from ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br /> julius Sat, 24 Mar 2012 18:13:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=788 Allow setting the boot address as an external parameter. If no ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=679 <div><strong>Rev 679 - olof</strong> (4 file(s) modified)</div><div>Allow setting the boot address as an external<br /> parameter. If no ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br /> olof Wed, 29 Feb 2012 18:04:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=679 atlys: add 2-clock synchronizer chain for ddr2_calib_done The signal ddr2_calib_done signal ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=677 <div><strong>Rev 677 - stekern</strong> (1 file(s) modified)</div><div>atlys: add 2-clock synchronizer chain for ddr2_calib_done<br /> <br /> The signal ddr2_calib_done signal ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br /> stekern Tue, 21 Feb 2012 16:01:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=677 Multiple 64-bit fixes (mostly sign and size of constants). Fix ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=673 <div><strong>Rev 673 - yannv</strong> (13 file(s) modified)</div><div>Multiple 64-bit fixes (mostly sign and size of constants). Fix ...</div>~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/binutils-2.18.50/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/binutils-2.20.1/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-6.8/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-7.1/opcodes/or32-opc.c<br />~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-dis.c<br />~ /openrisc/trunk/gnu-src/gdb-7.2/opcodes/or32-opc.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/or32.c<br />~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-dis.c<br />~ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-opc.c<br /> yannv Fri, 16 Dec 2011 13:58:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=673 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=672 <div><strong>Rev 672 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br /> julius Mon, 12 Dec 2011 22:32:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=672 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=671 <div><strong>Rev 671 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression ...</div>~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br /> julius Mon, 12 Dec 2011 22:14:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=671 minor corrections to clean simulation files https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=662 <div><strong>Rev 662 - paknick</strong> (1 file(s) modified)</div><div>minor corrections to clean simulation files</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-simclean.inc<br /> paknick Wed, 16 Nov 2011 17:27:17 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2F&rev=662

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