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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&
Thu, 28 Mar 2024 08:50:15 +0100
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orpsocv2: correct build/par issue on Atlys board
From patch submission e-mail:
The ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=866
<div><strong>Rev 866 - stekern</strong> (1 file(s) modified)</div><div>orpsocv2: correct build/par issue on Atlys board<br />
<br />
From patch submission e-mail:<br />
<br />
The ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />
stekern
Tue, 22 Apr 2014 05:19:09 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=866
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Add OR1200_OR32_LWS define to board specific or1200_defines.v
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=854
<div><strong>Rev 854 - stekern</strong> (4 file(s) modified)</div><div>Add OR1200_OR32_LWS define to board specific or1200_defines.v</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v<br />
stekern
Tue, 04 Dec 2012 04:27:31 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=854
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atlys: add 2-clock synchronizer chain for ddr2_calib_done
The signal ddr2_calib_done signal ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=677
<div><strong>Rev 677 - stekern</strong> (1 file(s) modified)</div><div>atlys: add 2-clock synchronizer chain for ddr2_calib_done<br />
<br />
The signal ddr2_calib_done signal ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />
stekern
Tue, 21 Feb 2012 16:01:04 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=677
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ORPSoC: add CFI flash controller to ml501, sw driver, tests, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=655
<div><strong>Rev 655 - julius</strong> (45 file(s) modified)</div><div>ORPSoC: add CFI flash controller to ml501, sw driver, tests, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_BankLib.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_CUIcommandData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_data.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_def.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_TimingData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_UserData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/x28fxxxp30.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-sim-definesgen.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-swrules.inc<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.c<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.ld<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include/cfi_ctrl.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/Makefile<br />
julius
Sat, 22 Oct 2011 20:32:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=655
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Fix make compile.tcl for actel backend
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=652
<div><strong>Rev 652 - yannv</strong> (1 file(s) modified)</div><div>Fix make compile.tcl for actel backend</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />
yannv
Fri, 14 Oct 2011 13:33:55 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=652
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orpsoc: xilinx: use XILINX env variable
instead of rely on custom ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=638
<div><strong>Rev 638 - stekern</strong> (9 file(s) modified)</div><div>orpsoc: xilinx: use XILINX env variable<br />
<br />
instead of rely on custom ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br />
stekern
Mon, 29 Aug 2011 03:19:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=638
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orpsoc: atlys: autoregenerate coregen cores
Instead of keeping binary .ngc files ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=634
<div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br />
<br />
Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br />
stekern
Wed, 24 Aug 2011 03:28:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=634
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orpsoc: add Digilent Atlys spartan6 board README
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=633
<div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br />
stekern
Wed, 24 Aug 2011 03:28:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=633
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orpsoc: add Digilent Atlys spartan6 board sw include file
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=632
<div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br />
<br />
Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br />
stekern
Wed, 24 Aug 2011 03:28:27 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=632
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orpsoc: add Digilent Atlys spartan6 board testbench
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=631
<div><strong>Rev 631 - stekern</strong> (12 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board testbench<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/bench/verilog/orpsoc_testbench.v<br />
stekern
Wed, 24 Aug 2011 03:28:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=631
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orpsoc: add Digilent Atlys spartan6 board backend
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=630
<div><strong>Rev 630 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board backend<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/atlys.ucf<br />
stekern
Wed, 24 Aug 2011 03:28:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=630
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orpsoc: add Digilent Atlys spartan6 board or1ksim configuration
Signed-off-by: Stefan ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=629
<div><strong>Rev 629 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board or1ksim configuration<br />
<br />
Signed-off-by: Stefan Kristiansson ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/atlys-or1ksim.cfg<br />
stekern
Wed, 24 Aug 2011 03:28:14 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=629
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orpsoc: add Digilent Atlys spartan6 board Makefiles
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=628
<div><strong>Rev 628 - stekern</strong> (22 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board Makefiles<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile<br />
stekern
Wed, 24 Aug 2011 03:28:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=628
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orpsoc: add Digilent Atlys spartan6 board rtl
Signed-off-by: Stefan Kristiansson ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=627
<div><strong>Rev 627 - stekern</strong> (42 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board rtl<br />
<br />
Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/lfsr/lfsr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v<br />
stekern
Wed, 24 Aug 2011 03:28:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=627
-
OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=568
<div><strong>Rev 568 - julius</strong> (115 file(s) modified)</div><div>OPRSoC - adding Xilinx Xtreme DSP Spartan-3A 1800A board port ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/bin/s3adsp_ddr2_cache.ngc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/s3adsp1800.ucf<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/prebuilt<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_parameters.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_preload.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/bench/verilog/orpsoc_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/modules<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/ethmac_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/s3adsp_ddr2_parameters_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cache.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_ctl.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_clk_dcm.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_controller_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_write_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_dqs_delay.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_0_wr_en_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_1_wr_en_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_top.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_iobs_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_ram8d_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_rd_gray_cntr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dm_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dqs_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dq_iob.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_tap_dly.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_top_0.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_wr_gray_cntr.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/out<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/bootrom.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-1.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-2.S<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/sw/tests/ethmac/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/out<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/run/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />
julius
Sat, 02 Jul 2011 10:28:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=568
-
Search for external cores in <board>/modules path
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=563
<div><strong>Rev 563 - olof</strong> (4 file(s) modified)</div><div>Search for external cores in <board>/modules path</div>+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/modules<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/modules<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-paths.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc<br />
olof
Sun, 19 Jun 2011 21:19:44 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=563
-
ORPSoC update - update make scripts, XILINX_PATH setup changes.
Note - ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=560
<div><strong>Rev 560 - julius</strong> (4 file(s) modified)</div><div>ORPSoC update - update make scripts, XILINX_PATH setup changes.<br />
<br />
Note - ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br />
julius
Sat, 11 Jun 2011 22:32:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=560
-
ORPSoC ordb1a3pe1500 update - adding SD card controller.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=544
<div><strong>Rev 544 - julius</strong> (25 file(s) modified)</div><div>ORPSoC ordb1a3pe1500 update - adding SD card controller.</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuexpio.mkpinassigns<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/sd_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sdc_controller.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_bd.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_clock_divider.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_cmd_master.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_cmd_serial_host.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_controller_wb.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_7.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_16.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_data_master.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_data_serial_host.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_fifo_rx_filler.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_fifo_tx_filler.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_rx_fifo.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_rx_fifo_tb.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_tx_fifo.v<br />
julius
Wed, 25 May 2011 09:37:59 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=544
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ORPSoC scripts cleanup. Now centralised.
Documentation updated for ml501's SPI ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=542
<div><strong>Rev 542 - julius</strong> (26 file(s) modified)</div><div>ORPSoC scripts cleanup. Now centralised. <br />
<br />
Documentation updated for ml501's SPI ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/scripts<br />+ /openrisc/trunk/orpsocv2/scripts/make<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-benchsrc.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-definesparse.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-paths.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-simclean.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-sw.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-tops.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-misc.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-rtltestrules.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-sim-definesgen.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-simulators.inc<br />+ /openrisc/trunk/orpsocv2/scripts/make/Makefile-swrules.inc<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/spiflash-program.c<br />
julius
Thu, 19 May 2011 19:43:58 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=542
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ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=530
<div><strong>Rev 530 - julius</strong> (27 file(s) modified)</div><div>ORPSoC update<br />
<br />
Ethernet MAC Wishbone interface fixes<br />
<br />
Beginnings of software update.<br />
<br />
ML501 backend ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/ethmac.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/cache.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxoverflow.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cy.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S<br />
julius
Tue, 26 Apr 2011 09:32:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fboards%2F&rev=530
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