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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Fusbhostslave%2FsendPacketArbiter.v& Thu, 28 Mar 2024 23:14:25 +0100 FeedCreator 1.7.2 ORPSoC update - adding support for ORSoC development board, many ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Fusbhostslave%2F&rev=408 <div><strong>Rev 408 - julius</strong> (295 file(s) modified)</div><div>ORPSoC update - adding support for ORSoC development board, many ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/directControl_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/dpMem_dc_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/endpMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoRTL_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/getPacket_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/HCTxPortArbiter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostcontroller_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMuxBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/lineControlUpdate_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxBit_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxByte_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processTxByte_simlib.v<br />+ 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/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16.fzm<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ddr.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_top.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_wb.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/out<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/bootrom.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-host.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-slave.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-host.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-slave.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/i2c_master_slave-loopback.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/usbhostslave-hostsimple.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/usbhostslave-slavesimple.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/out<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/run<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/run/Makefile<br />- /openrisc/trunk/orpsocv2/doc/config.log<br />- /openrisc/trunk/orpsocv2/doc/config.status<br />- /openrisc/trunk/orpsocv2/doc/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_bit_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_byte_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/README<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_constants_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_hostcontrol_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_hostslave_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_serialinterfaceengine_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_slavecontrol_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_wishbonebus_h.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/simple_spi.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_if.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_sync.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/directControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/dpMem_dc.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/endpMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/fifoMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/fifoRTL.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/getPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/HCTxPortArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostcontroller.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMuxBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/lineControlUpdate.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processRxBit.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processRxByte.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processTxByte.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/readUSBWireData.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/RxFifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/RxfifoBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/rxStatusMonitor.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SCTxPortArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacketArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacketCheckPreamble.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SIEReceiver.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SIETransmitter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slavecontroller.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveDirectControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveGetPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveRxStatusMonitor.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveSendPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SOFController.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SOFTransmit.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/speedCtrlMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/TxFifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/TxfifoBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/updateCRC5.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/updateCRC16.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbhost.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbHostControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBHostControlBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbhostslave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbSerialInterfaceEngine.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbslave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbSlaveControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBSlaveControlBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBTxWireArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/wishBoneBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/writeUSBWireData.v<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/spiflash-program.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/eth-phy-mii.h<br />~ /openrisc/trunk/orpsocv2/sw/tests/eth/board/eth-ping.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/open-eth.h<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board/uart-echo.c<br /> julius Wed, 03 Nov 2010 00:57:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Fusbhostslave%2F&rev=408
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