URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Error creating feed file, please check write permissions.
openrisc
WebSVN RSS feed - openrisc
https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&
Sat, 14 Mar 2026 13:59:27 +0100
FeedCreator 1.7.2
-
ORPSoC: Commit for bug 85 - add DSX support to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=807
<div><strong>Rev 807 - julius</strong> (6 file(s) modified)</div><div>ORPSoC: Commit for bug 85 - add DSX support to ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsx.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsxinsn.S<br />
julius
Sat, 26 May 2012 23:26:42 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=807
-
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=530
<div><strong>Rev 530 - julius</strong> (27 file(s) modified)</div><div>ORPSoC update<br />
<br />
Ethernet MAC Wishbone interface fixes<br />
<br />
Beginnings of software update.<br />
<br />
ML501 backend ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/ethmac.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/cache.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxoverflow.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cy.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S<br />
julius
Tue, 26 Apr 2011 09:32:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=530
-
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=502
<div><strong>Rev 502 - julius</strong> (14 file(s) modified)</div><div>ORPSoC update - or1200, ethmac Xilinx fifos<br />
or1200 in ORPSoC has ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/uart_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cy.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ov.S<br />
julius
Fri, 11 Mar 2011 18:47:48 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=502
-
ORPSoC's System C UART model can now accept input from ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=500
<div><strong>Rev 500 - julius</strong> (5 file(s) modified)</div><div>ORPSoC's System C UART model can now accept input from ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Thu, 10 Mar 2011 15:22:20 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=500
-
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=499
<div><strong>Rev 499 - julius</strong> (12 file(s) modified)</div><div>ORPSoC OR1200 updates - added l.ext instructions with tests, ammended ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ext.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S<br />
julius
Wed, 09 Mar 2011 22:18:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=499
-
ORPSoC updates - or1200 monitor now has separate defines file, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=485
<div><strong>Rev 485 - julius</strong> (33 file(s) modified)</div><div>ORPSoC updates - or1200 monitor now has separate defines file, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/utils/marksec<br />- /openrisc/trunk/orpsocv2/sw/utils/merge2srec<br />
julius
Fri, 04 Feb 2011 09:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=485
-
ORPSoC updates. Added 16kB cache options to OR1200, now as ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=476
<div><strong>Rev 476 - julius</strong> (6 file(s) modified)</div><div>ORPSoC updates. Added 16kB cache options to OR1200, now as ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 14 Jan 2011 12:42:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=476
-
ORPSoC main simulation makefile tidy up, addition of BSS test ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=475
<div><strong>Rev 475 - julius</strong> (8 file(s) modified)</div><div>ORPSoC main simulation makefile tidy up, addition of BSS test ...</div>+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/ordb1a3pe1500-or1ksim.cfg<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/ml501-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />+ /openrisc/trunk/orpsocv2/sim/bin/refdesign-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />
julius
Fri, 14 Jan 2011 10:09:21 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=475
-
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=468
<div><strong>Rev 468 - julius</strong> (14 file(s) modified)</div><div>ORPSoC update:<br />
Added USER_ELF and USER_VMEM options to reference design simulation ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Sun, 09 Jan 2011 08:57:32 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=468
-
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=449
<div><strong>Rev 449 - julius</strong> (12 file(s) modified)</div><div>ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.<br />
<br />
Replace use ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/README<br />
julius
Mon, 13 Dec 2010 19:01:07 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=449
-
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=435
<div><strong>Rev 435 - julius</strong> (15 file(s) modified)</div><div>ORPSoC updates<br />
OR1200 multiply/MAC/division unit update with serial multiply and <br />
divide ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mul.c<br />
julius
Tue, 30 Nov 2010 00:08:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=435
-
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=431
<div><strong>Rev 431 - julius</strong> (11 file(s) modified)</div><div>Updated and move OR1200 supplementary manual.<br />
<br />
or_debug_proxy GDB RSP interface fix.<br />
<br />
ORPSoC ...</div>~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />- /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt<br />- /openrisc/trunk/docs/openrisc1200_supplementary_prm.pdf<br />+ /openrisc/trunk/or1200/doc/openrisc1200_supplementary_prm.odt<br />+ /openrisc/trunk/or1200/doc/openrisc1200_supplementary_prm.pdf<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-simple.c<br />~ /openrisc/trunk/or_debug_proxy/ChangeLog<br />~ /openrisc/trunk/or_debug_proxy/src/gdb.c<br />
julius
Tue, 23 Nov 2010 16:38:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=431
-
ORPSoC update:
GDB servers in VPI and System C model updated ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=425
<div><strong>Rev 425 - julius</strong> (32 file(s) modified)</div><div>ORPSoC update:<br />
<br />
GDB servers in VPI and System C model updated ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/README<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/fail.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/random.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testfloat.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testFunction.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testLoops.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testsoftfloat.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/writeHex.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />
julius
Tue, 16 Nov 2010 23:49:00 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=425
-
Improved ethmac testbench and software.
Renamed some OR1200 library functions to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=411
<div><strong>Rev 411 - julius</strong> (19 file(s) modified)</div><div>Improved ethmac testbench and software.<br />
<br />
Renamed some OR1200 library functions to ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/bootrom.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_tt.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/definesgen.inc<br />~ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c<br />
julius
Thu, 04 Nov 2010 13:09:21 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=411
-
ORPSoC big upgrade - intermediate check in. Lots still missing. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=403
<div><strong>Rev 403 - julius</strong> (60 file(s) modified)</div><div>ORPSoC big upgrade - intermediate check in. Lots still missing. ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/orpsoc-testbench-defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/timescale.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/timescale.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_txrx.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />+ /openrisc/trunk/orpsocv2/sim/bin/definesgen.inc<br />- /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />- /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S<br />- /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/eth/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c<br />
julius
Mon, 01 Nov 2010 19:26:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=403
-
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=397
<div><strong>Rev 397 - julius</strong> (44 file(s) modified)</div><div>ORPSoCv2:<br />
<br />
doc/ path added, with Texinfo documentation. Still a work ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/Makefile<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v<br />+ /openrisc/trunk/orpsocv2/doc<br />+ /openrisc/trunk/orpsocv2/doc/aclocal.m4<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.0<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.1<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.2<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/requests<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.0<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.1<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.2<br />+ /openrisc/trunk/orpsocv2/doc/config.log<br />+ /openrisc/trunk/orpsocv2/doc/config.status<br />+ /openrisc/trunk/orpsocv2/doc/config.texi<br />+ /openrisc/trunk/orpsocv2/doc/configure<br />+ /openrisc/trunk/orpsocv2/doc/configure.in<br />+ /openrisc/trunk/orpsocv2/doc/fdl-1.2.texi<br />+ /openrisc/trunk/orpsocv2/doc/install-sh<br />+ /openrisc/trunk/orpsocv2/doc/Makefile<br />+ /openrisc/trunk/orpsocv2/doc/Makefile.am<br />+ /openrisc/trunk/orpsocv2/doc/Makefile.in<br />+ /openrisc/trunk/orpsocv2/doc/missing<br />+ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/doc/texinfo.tex<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c<br />
julius
Sat, 30 Oct 2010 13:51:16 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=397
-
ORPSoCv2 software rearrangement in progress. Basic tests should now run ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=393
<div><strong>Rev 393 - julius</strong> (131 file(s) modified)</div><div>ORPSoCv2 software rearrangement in progress. Basic tests should now run ...</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/apps<br />+ /openrisc/trunk/orpsocv2/sw/apps/dhry<br />+ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.h<br />+ /openrisc/trunk/orpsocv2/sw/apps/spiflash<br />+ /openrisc/trunk/orpsocv2/sw/apps/testfloat<br />+ /openrisc/trunk/orpsocv2/sw/board<br />+ /openrisc/trunk/orpsocv2/sw/board/include<br />+ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />- /openrisc/trunk/orpsocv2/sw/dhry<br />+ /openrisc/trunk/orpsocv2/sw/drivers<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/i2c_master_slave.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include/i2c_master_slave.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/spr-defs.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-mmu.S<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include/simple-spi.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/include/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />- /openrisc/trunk/orpsocv2/sw/include/board.h<br />- /openrisc/trunk/orpsocv2/sw/include/dhry.h<br />- /openrisc/trunk/orpsocv2/sw/include/int.h<br />- /openrisc/trunk/orpsocv2/sw/include/or32-utils.h<br />- /openrisc/trunk/orpsocv2/sw/include/printf.h<br />- /openrisc/trunk/orpsocv2/sw/include/simple-spi.h<br />- /openrisc/trunk/orpsocv2/sw/include/spr-defs.h<br />- /openrisc/trunk/orpsocv2/sw/include/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/lib<br />+ /openrisc/trunk/orpsocv2/sw/lib/include<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/cpu-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/lib-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/lib-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />- /openrisc/trunk/orpsocv2/sw/or1200/Makefile<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-cbasic.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-dctest.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-div.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-float.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-basic.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-except.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-fp.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-linkregtest.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-mac.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-ticksyscall.S<br />- /openrisc/trunk/orpsocv2/sw/sdram/Makefile<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-bankrows.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-banks.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-board-rows.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-cols.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-rows.c<br />- /openrisc/trunk/orpsocv2/sw/spi/Makefile<br />- /openrisc/trunk/orpsocv2/sw/spi/spi-interrupt.c<br />- /openrisc/trunk/orpsocv2/sw/spi/spi-simple.c<br />- /openrisc/trunk/orpsocv2/sw/spiflash<br />- /openrisc/trunk/orpsocv2/sw/support/crt0.S<br />- /openrisc/trunk/orpsocv2/sw/support/exceptions.c<br />- /openrisc/trunk/orpsocv2/sw/support/int.c<br />- /openrisc/trunk/orpsocv2/sw/support/or32-utils.c<br />- /openrisc/trunk/orpsocv2/sw/support/or32.ld<br />- /openrisc/trunk/orpsocv2/sw/support/or1200-mmu.S<br />- /openrisc/trunk/orpsocv2/sw/support/printf.c<br />- /openrisc/trunk/orpsocv2/sw/support/simple-spi.c<br />- /openrisc/trunk/orpsocv2/sw/support/uart.c<br />- /openrisc/trunk/orpsocv2/sw/testfloat<br />+ /openrisc/trunk/orpsocv2/sw/tests<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-banks.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram.h<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-simple.c<br />- /openrisc/trunk/orpsocv2/sw/uart/Makefile<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-echo.c<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-interrupt.c<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-simple.c<br />
julius
Wed, 27 Oct 2010 14:30:36 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=393
-
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=363
<div><strong>Rev 363 - julius</strong> (38 file(s) modified)</div><div>ORPSoC's RTL code fixed to pass linting by Verilator.<br />
<br />
ORPSoC's debug ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />
julius
Sun, 12 Sep 2010 07:57:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=363
-
ORPSoCv2 verilator building working again. Board build fixes to follow
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=362
<div><strong>Rev 362 - julius</strong> (7 file(s) modified)</div><div>ORPSoCv2 verilator building working again. Board build fixes to follow</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 10 Sep 2010 22:42:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=362
-
First checkin of new ORPSoC set up - more to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=360
<div><strong>Rev 360 - julius</strong> (94 file(s) modified)</div><div>First checkin of new ORPSoC set up - more to ...</div>- /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines_old.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_register.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth<br />- /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_startup<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_top<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/spi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/raminfr.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart16550.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_sdram_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_switch_b3<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/out<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Fri, 10 Sep 2010 17:51:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2F&rev=360
© copyright 1999-2026
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.