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s6soc WebSVN RSS feed - s6soc https://opencores.org/websvn//websvn/listing?repname=s6soc&path=%2Fs6soc%2F& Thu, 05 Mar 2026 14:02:10 +0100 FeedCreator 1.7.2 Modified the loader so that it will load even if ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=14 <div><strong>Rev 14 - dgisselq</strong> (2 file(s) modified)</div><div>Modified the loader so that it will load even if ...</div>~ /s6soc/trunk/sw/host/flashdrvr.cpp<br />~ /s6soc/trunk/sw/host/zipload.cpp<br /> dgisselq Sat, 30 Apr 2016 21:46:33 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=14 Fixed a nasty parameter problem between toplevel and txuart. ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=13 <div><strong>Rev 13 - dgisselq</strong> (6 file(s) modified)</div><div>Fixed a nasty parameter problem between toplevel and txuart. ...</div>~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/alttop.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/toplevel.v<br />~ /s6soc/trunk/rtl/txuart.v<br /> dgisselq Sat, 30 Apr 2016 21:41:23 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=13 The UART and PWM audio now work. This includes ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=12 <div><strong>Rev 12 - dgisselq</strong> (19 file(s) modified)</div><div>The UART and PWM audio now work. This includes ...</div>~ /s6soc/trunk/cmod.ucf<br />~ /s6soc/trunk/cmodtop.ucf<br />~ /s6soc/trunk/doc/gfx/pinout.eps<br />~ /s6soc/trunk/doc/gfx/pmodmap.eps<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/toplevel.v<br />~ /s6soc/trunk/rtl/wbpwmaudio.v<br />+ /s6soc/trunk/sw/dev<br />+ /s6soc/trunk/sw/dev/asmstartup.h<br />+ /s6soc/trunk/sw/dev/board.h<br />+ /s6soc/trunk/sw/dev/cmod.ld<br />+ /s6soc/trunk/sw/dev/doorbell.c<br />+ /s6soc/trunk/sw/dev/helloworld.c<br />+ /s6soc/trunk/sw/dev/Makefile<br />+ /s6soc/trunk/sw/dev/samples.c<br />+ /s6soc/trunk/sw/host/buildsamples.cpp<br />~ /s6soc/trunk/sw/host/Makefile<br />~ /s6soc/trunk/sw/host/regdefs.h<br />~ /s6soc/trunk/sw/Makefile<br /> dgisselq Sat, 30 Apr 2016 00:00:49 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=12 Runs on hardware now! Added proper pinouts, pipelined wishbone ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=11 <div><strong>Rev 11 - dgisselq</strong> (25 file(s) modified)</div><div>Runs on hardware now! Added proper pinouts, pipelined wishbone ...</div>~ /s6soc/trunk/cmod.ucf<br />+ /s6soc/trunk/cmodtop.ucf<br />~ /s6soc/trunk/Makefile<br />~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/idecode.v<br />~ /s6soc/trunk/rtl/cpu/zipcpu.v<br />+ /s6soc/trunk/rtl/deppbyte.v<br />~ /s6soc/trunk/rtl/wbqspiflash.v<br />+ /s6soc/trunk/sw/host/deppi.cpp<br />+ /s6soc/trunk/sw/host/deppi.h<br />~ /s6soc/trunk/sw/host/devbus.h<br />~ /s6soc/trunk/sw/host/flashdrvr.cpp<br />~ /s6soc/trunk/sw/host/flashdrvr.h<br />+ /s6soc/trunk/sw/host/llcomms.cpp<br />+ /s6soc/trunk/sw/host/llcomms.h<br />~ /s6soc/trunk/sw/host/Makefile<br />+ /s6soc/trunk/sw/host/readflash.cpp<br />~ /s6soc/trunk/sw/host/regdefs.h<br />+ /s6soc/trunk/sw/host/ttybus.cpp<br />+ /s6soc/trunk/sw/host/ttybus.h<br />~ /s6soc/trunk/sw/host/wbregs.cpp<br />+ /s6soc/trunk/sw/host/zipload.cpp<br />+ /s6soc/trunk/sw/Makefile<br /> dgisselq Fri, 29 Apr 2016 02:01:35 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=11 Added the capability to run ELF files natively, fully processing ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=10 <div><strong>Rev 10 - dgisselq</strong> (4 file(s) modified)</div><div>Added the capability to run ELF files natively, fully processing ...</div>~ /s6soc/trunk/bench/cpp/Makefile<br />~ /s6soc/trunk/bench/cpp/qspiflashsim.cpp<br />~ /s6soc/trunk/bench/cpp/qspiflashsim.h<br />~ /s6soc/trunk/bench/cpp/zip_sim.cpp<br /> dgisselq Fri, 29 Apr 2016 01:57:32 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=10 Added pinout diagrams, based upon a (hopefully) final UCF file. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=9 <div><strong>Rev 9 - dgisselq</strong> (2 file(s) modified)</div><div>Added pinout diagrams, based upon a (hopefully) final UCF file.</div>+ /s6soc/trunk/doc/gfx/pinout.eps<br />+ /s6soc/trunk/doc/gfx/pmodmap.eps<br /> dgisselq Fri, 29 Apr 2016 01:56:38 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=9 First pseudo-running version. The alternate configuration (not the main ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=8 <div><strong>Rev 8 - dgisselq</strong> (26 file(s) modified)</div><div>First pseudo-running version. The alternate configuration (not the main ...</div>~ /s6soc/trunk/cmod.ucf<br />~ /s6soc/trunk/Makefile<br />~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/alttop.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/ziptimer.v<br />+ /s6soc/trunk/rtl/Makefile<br />~ /s6soc/trunk/rtl/rtclight.v<br />~ /s6soc/trunk/rtl/spio.v<br />+ /s6soc/trunk/rtl/wbdeppsimple.v<br />~ /s6soc/trunk/rtl/wbpwmaudio.v<br />~ /s6soc/trunk/rtl/wbqspiflash.v<br />+ /s6soc/trunk/sw<br />+ /s6soc/trunk/sw/host<br />+ /s6soc/trunk/sw/host/deppbus.cpp<br />+ /s6soc/trunk/sw/host/deppbus.h<br />+ /s6soc/trunk/sw/host/devbus.h<br />+ /s6soc/trunk/sw/host/flashdrvr.cpp<br />+ /s6soc/trunk/sw/host/flashdrvr.h<br />+ /s6soc/trunk/sw/host/Makefile<br />+ /s6soc/trunk/sw/host/regdefs.cpp<br />+ /s6soc/trunk/sw/host/regdefs.h<br />+ /s6soc/trunk/sw/host/twoc.cpp<br />+ /s6soc/trunk/sw/host/twoc.h<br />+ /s6soc/trunk/sw/host/wbregs.cpp<br /> dgisselq Sun, 24 Apr 2016 01:26:43 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=8 Created/added an initial specification. Updated/corrected several copywrite notices. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=7 <div><strong>Rev 7 - dgisselq</strong> (21 file(s) modified)</div><div>Created/added an initial specification. Updated/corrected several copywrite<br /> notices.</div>+ /s6soc/trunk/doc<br />+ /s6soc/trunk/doc/gfx<br />+ /s6soc/trunk/doc/gfx/altbones.eps<br />+ /s6soc/trunk/doc/gfx/s6bones.eps<br />+ /s6soc/trunk/doc/gpl-3.0.pdf<br />+ /s6soc/trunk/doc/Makefile<br />+ /s6soc/trunk/doc/spec.pdf<br />+ /s6soc/trunk/doc/src<br />+ /s6soc/trunk/doc/src/gpl-3.0.tex<br />+ /s6soc/trunk/doc/src/gqtekspec.cls<br />+ /s6soc/trunk/doc/src/GT.eps<br />+ /s6soc/trunk/doc/src/spec.tex<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/cpudefs.v<br />~ /s6soc/trunk/rtl/cpu/cpuops.v<br />~ /s6soc/trunk/rtl/cpu/zipcpu.v<br />~ /s6soc/trunk/rtl/memdev.v<br />~ /s6soc/trunk/rtl/rtclight.v<br />~ /s6soc/trunk/rtl/spio.v<br />~ /s6soc/trunk/rtl/wbgpio.v<br /> dgisselq Sat, 23 Apr 2016 10:37:41 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=7 Initial UCF modifications. Pin layout still isn't complete, but ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=6 <div><strong>Rev 6 - dgisselq</strong> (2 file(s) modified)</div><div>Initial UCF modifications. Pin layout still isn't complete, but ...</div>~ /s6soc/trunk/cmod.ucf<br />~ /s6soc/trunk/Makefile<br /> dgisselq Sat, 02 Apr 2016 15:39:53 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=6 These two are my first attempt(s) at a secondary project ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=5 <div><strong>Rev 5 - dgisselq</strong> (2 file(s) modified)</div><div>These two are my first attempt(s) at a secondary project ...</div>+ /s6soc/trunk/rtl/altbusmaster.v<br />+ /s6soc/trunk/rtl/alttop.v<br /> dgisselq Sat, 02 Apr 2016 15:38:50 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=5 Lots of updates, as part of actually making this work ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=4 <div><strong>Rev 4 - dgisselq</strong> (9 file(s) modified)</div><div>Lots of updates, as part of actually making this work ...</div>~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/ziptimer.v<br />~ /s6soc/trunk/rtl/rtclight.v<br />~ /s6soc/trunk/rtl/rxuart.v<br />~ /s6soc/trunk/rtl/toplevel.v<br />~ /s6soc/trunk/rtl/txuart.v<br />~ /s6soc/trunk/rtl/wbpwmaudio.v<br />+ /s6soc/trunk/rtl/wbqspiflashp.v<br />+ /s6soc/trunk/rtl/wbubus.v<br /> dgisselq Sat, 02 Apr 2016 15:37:53 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=4 Updated date. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=3 <div><strong>Rev 3 - dgisselq</strong> (1 file(s) modified)</div><div>Updated date.</div>~ /s6soc/trunk/rtl/builddate.v<br /> dgisselq Sat, 02 Apr 2016 15:37:20 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=3 The initial check in--all the files that will make this ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=2 <div><strong>Rev 2 - dgisselq</strong> (47 file(s) modified)</div><div>The initial check in--all the files that will make this ...</div>+ /s6soc/trunk/bench<br />+ /s6soc/trunk/bench/cpp<br />+ /s6soc/trunk/bench/cpp/Makefile<br />+ /s6soc/trunk/bench/cpp/qspiflashsim.cpp<br />+ /s6soc/trunk/bench/cpp/qspiflashsim.h<br />+ /s6soc/trunk/bench/cpp/testb.h<br />+ /s6soc/trunk/bench/cpp/twoc.cpp<br />+ /s6soc/trunk/bench/cpp/twoc.h<br />+ /s6soc/trunk/bench/cpp/uartsim.cpp<br />+ /s6soc/trunk/bench/cpp/uartsim.h<br />+ /s6soc/trunk/bench/cpp/zip_sim.cpp<br />+ /s6soc/trunk/cmod.ucf<br />+ /s6soc/trunk/Makefile<br />+ /s6soc/trunk/mkdatev.pl<br />+ /s6soc/trunk/rtl<br />+ /s6soc/trunk/rtl/builddate.v<br />+ /s6soc/trunk/rtl/busmaster.v<br />+ /s6soc/trunk/rtl/cpu<br />+ /s6soc/trunk/rtl/cpu/busdelay.v<br />+ /s6soc/trunk/rtl/cpu/cpudefs.v<br />+ /s6soc/trunk/rtl/cpu/cpuops.v<br />+ /s6soc/trunk/rtl/cpu/icontrol.v<br />+ /s6soc/trunk/rtl/cpu/idecode.v<br />+ /s6soc/trunk/rtl/cpu/memops.v<br />+ /s6soc/trunk/rtl/cpu/prefetch.v<br />+ /s6soc/trunk/rtl/cpu/wbarbiter.v<br />+ /s6soc/trunk/rtl/cpu/wbdblpriarb.v<br />+ /s6soc/trunk/rtl/cpu/wbpriarbiter.v<br />+ /s6soc/trunk/rtl/cpu/zipbones.v<br />+ /s6soc/trunk/rtl/cpu/zipcpu.v<br />+ /s6soc/trunk/rtl/cpu/ziptimer.v<br />+ /s6soc/trunk/rtl/flashconfig.v<br />+ /s6soc/trunk/rtl/flash_config.v<br />+ /s6soc/trunk/rtl/llqspi.v<br />+ /s6soc/trunk/rtl/memdev.v<br />+ /s6soc/trunk/rtl/rtcdate.v<br />+ /s6soc/trunk/rtl/rtclight.v<br />+ /s6soc/trunk/rtl/rxuart.v<br />+ /s6soc/trunk/rtl/spio.v<br />+ /s6soc/trunk/rtl/toplevel.v<br />+ /s6soc/trunk/rtl/txuart.v<br />+ /s6soc/trunk/rtl/wbgpio.v<br />+ /s6soc/trunk/rtl/wbicape6.v<br />+ /s6soc/trunk/rtl/wbicapesimple.v<br />+ /s6soc/trunk/rtl/wbpwmaudio.v<br />+ /s6soc/trunk/rtl/wbqspiflash.v<br />+ /s6soc/trunk/rtl/wbscope.v<br /> dgisselq Tue, 22 Mar 2016 20:37:28 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=2 The project and the structure was created https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=1 <div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /s6soc<br />+ /s6soc/branches<br />+ /s6soc/tags<br />+ /s6soc/trunk<br /> root Tue, 22 Mar 2016 19:15:03 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=1

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