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s6soc WebSVN RSS feed - s6soc https://opencores.org/websvn//websvn/listing?repname=s6soc&path=%2Fs6soc%2F& Thu, 28 Mar 2024 11:06:17 +0100 FeedCreator 1.7.2 Added a bootloader capability so that pieces of the program ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=27 <div><strong>Rev 27 - dgisselq</strong> (11 file(s) modified)</div><div>Added a bootloader capability so that pieces of the program ...</div>+ /s6soc/trunk/sw/zipos/bootloader.c<br />+ /s6soc/trunk/sw/zipos/cmodram.ld<br />~ /s6soc/trunk/sw/zipos/doorbell.c<br />~ /s6soc/trunk/sw/zipos/kernel.c<br />+ /s6soc/trunk/sw/zipos/ksetup.c<br />~ /s6soc/trunk/sw/zipos/Makefile<br />+ /s6soc/trunk/sw/zipos/pipesetup.c<br />~ /s6soc/trunk/sw/zipos/resetdump.s<br />~ /s6soc/trunk/sw/zipos/syspipe.c<br />~ /s6soc/trunk/sw/zipos/syspipe.h<br />~ /s6soc/trunk/sw/zipos/zipsys.h<br /> dgisselq Tue, 10 May 2016 14:33:05 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=27 Modified to be able to handle different load from virtual ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=26 <div><strong>Rev 26 - dgisselq</strong> (1 file(s) modified)</div><div>Modified to be able to handle different load from virtual ...</div>~ /s6soc/trunk/sw/host/zipload.cpp<br /> dgisselq Tue, 10 May 2016 14:30:27 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=26 Converted timer B to be a non-reloadable watchdog timer. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=25 <div><strong>Rev 25 - dgisselq</strong> (2 file(s) modified)</div><div>Converted timer B to be a non-reloadable watchdog timer.</div>~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/busmaster.v<br /> dgisselq Tue, 10 May 2016 14:28:59 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=25 Made the ziptimer autoreload feature a parameter (dis)abled option. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=24 <div><strong>Rev 24 - dgisselq</strong> (1 file(s) modified)</div><div>Made the ziptimer autoreload feature a parameter (dis)abled option.</div>~ /s6soc/trunk/rtl/cpu/ziptimer.v<br /> dgisselq Tue, 10 May 2016 14:13:54 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=24 Fixed a bug which caused every instruction to be loaded/prefetched ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=23 <div><strong>Rev 23 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed a bug which caused every instruction to be loaded/prefetched ...</div>~ /s6soc/trunk/rtl/cpu/zipcpu.v<br /> dgisselq Tue, 10 May 2016 14:12:42 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=23 Initial version of the ZipOS operating system construct(s). https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=22 <div><strong>Rev 22 - dgisselq</strong> (20 file(s) modified)</div><div>Initial version of the ZipOS operating system construct(s).</div>+ /s6soc/trunk/sw/zipos<br />+ /s6soc/trunk/sw/zipos/board.h<br />+ /s6soc/trunk/sw/zipos/cmod.ld<br />+ /s6soc/trunk/sw/zipos/doorbell.c<br />+ /s6soc/trunk/sw/zipos/errno.h<br />+ /s6soc/trunk/sw/zipos/kernel.c<br />+ /s6soc/trunk/sw/zipos/kfildes.h<br />+ /s6soc/trunk/sw/zipos/ksched.h<br />+ /s6soc/trunk/sw/zipos/ktraps.h<br />+ /s6soc/trunk/sw/zipos/Makefile<br />+ /s6soc/trunk/sw/zipos/resetdump.s<br />+ /s6soc/trunk/sw/zipos/swint.h<br />+ /s6soc/trunk/sw/zipos/syspipe.c<br />+ /s6soc/trunk/sw/zipos/syspipe.h<br />+ /s6soc/trunk/sw/zipos/taskp.c<br />+ /s6soc/trunk/sw/zipos/taskp.h<br />+ /s6soc/trunk/sw/zipos/ziplib.c<br />+ /s6soc/trunk/sw/zipos/ziplib.h<br />+ /s6soc/trunk/sw/zipos/zipsys.c<br />+ /s6soc/trunk/sw/zipos/zipsys.h<br /> dgisselq Fri, 06 May 2016 16:03:08 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=22 Adds two device drivers: one for the SPI display, and ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=21 <div><strong>Rev 21 - dgisselq</strong> (4 file(s) modified)</div><div>Adds two device drivers: one for the SPI display, and ...</div>~ /s6soc/trunk/sw/dev/display.c<br />~ /s6soc/trunk/sw/dev/display.h<br />~ /s6soc/trunk/sw/dev/rtcsim.c<br />~ /s6soc/trunk/sw/dev/rtcsim.h<br /> dgisselq Fri, 06 May 2016 15:27:02 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=21 This linker description file acknowledges a .fixdata section which can ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=20 <div><strong>Rev 20 - dgisselq</strong> (1 file(s) modified)</div><div>This linker description file acknowledges a .fixdata section which can ...</div>~ /s6soc/trunk/sw/dev/cmod.ld<br /> dgisselq Fri, 06 May 2016 15:24:42 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=20 Addition of dumpuart.cpp to dump the UART transactions to a ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=19 <div><strong>Rev 19 - dgisselq</strong> (4 file(s) modified)</div><div>Addition of dumpuart.cpp to dump the UART transactions to a ...</div>+ /s6soc/trunk/sw/host/dumpuart.cpp<br />~ /s6soc/trunk/sw/host/flashdrvr.cpp<br />~ /s6soc/trunk/sw/host/Makefile<br />~ /s6soc/trunk/sw/host/zipload.cpp<br /> dgisselq Fri, 06 May 2016 15:23:08 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=19 Added a picture of the device pinouts to the specification. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=18 <div><strong>Rev 18 - dgisselq</strong> (3 file(s) modified)</div><div>Added a picture of the device pinouts to the specification.</div>~ /s6soc/trunk/doc/gfx/pinout.eps<br />~ /s6soc/trunk/doc/spec.pdf<br />~ /s6soc/trunk/doc/src/spec.tex<br /> dgisselq Fri, 06 May 2016 15:18:20 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=18 Modifications necessary to find some bugs, and to load the ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=17 <div><strong>Rev 17 - dgisselq</strong> (2 file(s) modified)</div><div>Modifications necessary to find some bugs, and to load the ...</div>~ /s6soc/trunk/bench/cpp/qspiflashsim.cpp<br />~ /s6soc/trunk/bench/cpp/zip_sim.cpp<br /> dgisselq Fri, 06 May 2016 15:09:51 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=17 Bug fix. This release fixes several bugs associated with ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=16 <div><strong>Rev 16 - dgisselq</strong> (7 file(s) modified)</div><div>Bug fix. This release fixes several bugs associated with ...</div>~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/cpudefs.v<br />~ /s6soc/trunk/rtl/cpu/cpuops.v<br />~ /s6soc/trunk/rtl/cpu/zipcpu.v<br />~ /s6soc/trunk/rtl/cpu/ziptimer.v<br />+ /s6soc/trunk/rtl/wbscopc.v<br /> dgisselq Fri, 06 May 2016 15:07:13 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=16 Adds a new program and a new device: doorbell2 and ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=15 <div><strong>Rev 15 - dgisselq</strong> (8 file(s) modified)</div><div>Adds a new program and a new device: doorbell2 and ...</div>~ /s6soc/trunk/sw/dev/board.h<br />+ /s6soc/trunk/sw/dev/display.c<br />+ /s6soc/trunk/sw/dev/display.h<br />~ /s6soc/trunk/sw/dev/doorbell.c<br />+ /s6soc/trunk/sw/dev/doorbell2.c<br />~ /s6soc/trunk/sw/dev/Makefile<br />+ /s6soc/trunk/sw/dev/rtcsim.c<br />+ /s6soc/trunk/sw/dev/rtcsim.h<br /> dgisselq Sat, 30 Apr 2016 21:48:34 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=15 Modified the loader so that it will load even if ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=14 <div><strong>Rev 14 - dgisselq</strong> (2 file(s) modified)</div><div>Modified the loader so that it will load even if ...</div>~ /s6soc/trunk/sw/host/flashdrvr.cpp<br />~ /s6soc/trunk/sw/host/zipload.cpp<br /> dgisselq Sat, 30 Apr 2016 21:46:33 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=14 Fixed a nasty parameter problem between toplevel and txuart. ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=13 <div><strong>Rev 13 - dgisselq</strong> (6 file(s) modified)</div><div>Fixed a nasty parameter problem between toplevel and txuart. ...</div>~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/alttop.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/toplevel.v<br />~ /s6soc/trunk/rtl/txuart.v<br /> dgisselq Sat, 30 Apr 2016 21:41:23 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=13 The UART and PWM audio now work. This includes ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=12 <div><strong>Rev 12 - dgisselq</strong> (19 file(s) modified)</div><div>The UART and PWM audio now work. This includes ...</div>~ /s6soc/trunk/cmod.ucf<br />~ /s6soc/trunk/cmodtop.ucf<br />~ /s6soc/trunk/doc/gfx/pinout.eps<br />~ /s6soc/trunk/doc/gfx/pmodmap.eps<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/toplevel.v<br />~ /s6soc/trunk/rtl/wbpwmaudio.v<br />+ /s6soc/trunk/sw/dev<br />+ /s6soc/trunk/sw/dev/asmstartup.h<br />+ /s6soc/trunk/sw/dev/board.h<br />+ /s6soc/trunk/sw/dev/cmod.ld<br />+ /s6soc/trunk/sw/dev/doorbell.c<br />+ /s6soc/trunk/sw/dev/helloworld.c<br />+ /s6soc/trunk/sw/dev/Makefile<br />+ /s6soc/trunk/sw/dev/samples.c<br />+ /s6soc/trunk/sw/host/buildsamples.cpp<br />~ /s6soc/trunk/sw/host/Makefile<br />~ /s6soc/trunk/sw/host/regdefs.h<br />~ /s6soc/trunk/sw/Makefile<br /> dgisselq Sat, 30 Apr 2016 00:00:49 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=12 Runs on hardware now! Added proper pinouts, pipelined wishbone ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=11 <div><strong>Rev 11 - dgisselq</strong> (25 file(s) modified)</div><div>Runs on hardware now! Added proper pinouts, pipelined wishbone ...</div>~ /s6soc/trunk/cmod.ucf<br />+ /s6soc/trunk/cmodtop.ucf<br />~ /s6soc/trunk/Makefile<br />~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/idecode.v<br />~ /s6soc/trunk/rtl/cpu/zipcpu.v<br />+ /s6soc/trunk/rtl/deppbyte.v<br />~ /s6soc/trunk/rtl/wbqspiflash.v<br />+ /s6soc/trunk/sw/host/deppi.cpp<br />+ /s6soc/trunk/sw/host/deppi.h<br />~ /s6soc/trunk/sw/host/devbus.h<br />~ /s6soc/trunk/sw/host/flashdrvr.cpp<br />~ /s6soc/trunk/sw/host/flashdrvr.h<br />+ /s6soc/trunk/sw/host/llcomms.cpp<br />+ /s6soc/trunk/sw/host/llcomms.h<br />~ /s6soc/trunk/sw/host/Makefile<br />+ /s6soc/trunk/sw/host/readflash.cpp<br />~ /s6soc/trunk/sw/host/regdefs.h<br />+ /s6soc/trunk/sw/host/ttybus.cpp<br />+ /s6soc/trunk/sw/host/ttybus.h<br />~ /s6soc/trunk/sw/host/wbregs.cpp<br />+ /s6soc/trunk/sw/host/zipload.cpp<br />+ /s6soc/trunk/sw/Makefile<br /> dgisselq Fri, 29 Apr 2016 02:01:35 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=11 Added the capability to run ELF files natively, fully processing ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=10 <div><strong>Rev 10 - dgisselq</strong> (4 file(s) modified)</div><div>Added the capability to run ELF files natively, fully processing ...</div>~ /s6soc/trunk/bench/cpp/Makefile<br />~ /s6soc/trunk/bench/cpp/qspiflashsim.cpp<br />~ /s6soc/trunk/bench/cpp/qspiflashsim.h<br />~ /s6soc/trunk/bench/cpp/zip_sim.cpp<br /> dgisselq Fri, 29 Apr 2016 01:57:32 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=10 Added pinout diagrams, based upon a (hopefully) final UCF file. https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=9 <div><strong>Rev 9 - dgisselq</strong> (2 file(s) modified)</div><div>Added pinout diagrams, based upon a (hopefully) final UCF file.</div>+ /s6soc/trunk/doc/gfx/pinout.eps<br />+ /s6soc/trunk/doc/gfx/pmodmap.eps<br /> dgisselq Fri, 29 Apr 2016 01:56:38 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=9 First pseudo-running version. The alternate configuration (not the main ... https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=8 <div><strong>Rev 8 - dgisselq</strong> (26 file(s) modified)</div><div>First pseudo-running version. The alternate configuration (not the main ...</div>~ /s6soc/trunk/cmod.ucf<br />~ /s6soc/trunk/Makefile<br />~ /s6soc/trunk/rtl/altbusmaster.v<br />~ /s6soc/trunk/rtl/alttop.v<br />~ /s6soc/trunk/rtl/builddate.v<br />~ /s6soc/trunk/rtl/busmaster.v<br />~ /s6soc/trunk/rtl/cpu/ziptimer.v<br />+ /s6soc/trunk/rtl/Makefile<br />~ /s6soc/trunk/rtl/rtclight.v<br />~ /s6soc/trunk/rtl/spio.v<br />+ /s6soc/trunk/rtl/wbdeppsimple.v<br />~ /s6soc/trunk/rtl/wbpwmaudio.v<br />~ /s6soc/trunk/rtl/wbqspiflash.v<br />+ /s6soc/trunk/sw<br />+ /s6soc/trunk/sw/host<br />+ /s6soc/trunk/sw/host/deppbus.cpp<br />+ /s6soc/trunk/sw/host/deppbus.h<br />+ /s6soc/trunk/sw/host/devbus.h<br />+ /s6soc/trunk/sw/host/flashdrvr.cpp<br />+ /s6soc/trunk/sw/host/flashdrvr.h<br />+ /s6soc/trunk/sw/host/Makefile<br />+ /s6soc/trunk/sw/host/regdefs.cpp<br />+ /s6soc/trunk/sw/host/regdefs.h<br />+ /s6soc/trunk/sw/host/twoc.cpp<br />+ /s6soc/trunk/sw/host/twoc.h<br />+ /s6soc/trunk/sw/host/wbregs.cpp<br /> dgisselq Sun, 24 Apr 2016 01:26:43 +0100 https://opencores.org/websvn//websvn/revision?repname=s6soc&path=%2Fs6soc%2F&rev=8
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