URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Error creating feed file, please check write permissions.
sdr_ctrl
WebSVN RSS feed - sdr_ctrl
https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&
Thu, 28 Mar 2024 19:19:47 +0100
FeedCreator 1.7.2
-
Port cleanup
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=15
<div><strong>Rev 15 - dinesha</strong> (4 file(s) modified)</div><div>Port cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />
dinesha
Sat, 21 Jan 2012 13:16:56 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=15
-
Unnecessary device config are removed
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=14
<div><strong>Rev 14 - dinesha</strong> (1 file(s) modified)</div><div>Unnecessary device config are removed</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Sat, 21 Jan 2012 13:10:33 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=14
-
column bit are made progrmmable
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=13
<div><strong>Rev 13 - dinesha</strong> (3 file(s) modified)</div><div>column bit are made progrmmable</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />
dinesha
Sat, 21 Jan 2012 12:56:43 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=13
-
Column Bits are made programmable
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=12
<div><strong>Rev 12 - dinesha</strong> (1 file(s) modified)</div><div>Column Bits are made programmable</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Sat, 21 Jan 2012 12:53:26 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=12
-
SDRAM Specification document added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=11
<div><strong>Rev 11 - dinesha</strong> (1 file(s) modified)</div><div>SDRAM Specification document added into SVN</div>+ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br />
dinesha
Wed, 18 Jan 2012 12:02:44 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=11
-
Waveform files are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=10
<div><strong>Rev 10 - dinesha</strong> (6 file(s) modified)</div><div>Waveform files are added into SVN</div>+ /sdr_ctrl/trunk/verif/dump/Application-ReadRequest.jpg<br />+ /sdr_ctrl/trunk/verif/dump/Application-WriteRequest.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-16Bit-Read-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-16Bit-Write-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-32Bit-Read-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-32Bit-Write-Transaction.jpg<br />
dinesha
Wed, 18 Jan 2012 11:57:17 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=10
-
SDR Bus width parameter passing issue across the models are ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=9
<div><strong>Rev 9 - dinesha</strong> (1 file(s) modified)</div><div>SDR Bus width parameter passing issue across the models are ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Tue, 17 Jan 2012 12:13:44 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=9
-
test bench files are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=8
<div><strong>Rev 8 - dinesha</strong> (1 file(s) modified)</div><div>test bench files are added into SVN</div>+ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Tue, 17 Jan 2012 12:11:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=8
-
SDRAM Memory Models are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=7
<div><strong>Rev 7 - dinesha</strong> (4 file(s) modified)</div><div>SDRAM Memory Models are added into SVN</div>+ /sdr_ctrl/trunk/verif/model/IS42VM16400K.V<br />+ /sdr_ctrl/trunk/verif/model/mt48lc2m32b2.v<br />+ /sdr_ctrl/trunk/verif/model/mt48lc4m16.v<br />+ /sdr_ctrl/trunk/verif/model/mt48lc4m32b2.v<br />
dinesha
Tue, 17 Jan 2012 12:08:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=7
-
Golden Log files are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=6
<div><strong>Rev 6 - dinesha</strong> (6 file(s) modified)</div><div>Golden Log files are added into SVN</div>+ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Tue, 17 Jan 2012 12:00:29 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=6
-
Run files are updated into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=5
<div><strong>Rev 5 - dinesha</strong> (6 file(s) modified)</div><div>Run files are updated into SVN</div>+ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist.f<br />+ /sdr_ctrl/trunk/verif/run/read.me<br />+ /sdr_ctrl/trunk/verif/run/run.do<br />+ /sdr_ctrl/trunk/verif/run/run_all<br />+ /sdr_ctrl/trunk/verif/run/run_modelsim<br />
dinesha
Tue, 17 Jan 2012 11:59:49 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=5
-
Sdram controller RTL bug fixes done for 16bit SDR Mode
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=4
<div><strong>Rev 4 - dinesha</strong> (4 file(s) modified)</div><div>Sdram controller RTL bug fixes done for 16bit SDR Mode</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Mon, 16 Jan 2012 14:54:21 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=4
-
SDRAM controller core files are checked in
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=3
<div><strong>Rev 3 - dinesha</strong> (7 file(s) modified)</div><div>SDRAM controller core files are checked in</div>+ /sdr_ctrl/trunk/rtl/core<br />+ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />
dinesha
Tue, 10 Jan 2012 04:39:31 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=3
-
...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=2
<div><strong>Rev 2 - dinesha</strong> (16 file(s) modified)</div><div>...</div>+ /sdr_ctrl/trunk/doc<br />+ /sdr_ctrl/trunk/env<br />+ /sdr_ctrl/trunk/models<br />+ /sdr_ctrl/trunk/rtl<br />+ /sdr_ctrl/trunk/rtl/defs<br />+ /sdr_ctrl/trunk/rtl/lib<br />+ /sdr_ctrl/trunk/verif<br />+ /sdr_ctrl/trunk/verif/agents<br />+ /sdr_ctrl/trunk/verif/defs<br />+ /sdr_ctrl/trunk/verif/dump<br />+ /sdr_ctrl/trunk/verif/lib<br />+ /sdr_ctrl/trunk/verif/log<br />+ /sdr_ctrl/trunk/verif/model<br />+ /sdr_ctrl/trunk/verif/run<br />+ /sdr_ctrl/trunk/verif/tb<br />+ /sdr_ctrl/trunk/verif/test_case<br />
dinesha
Sat, 07 Jan 2012 12:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=2
-
The project and the structure was created
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=1
<div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /sdr_ctrl<br />+ /sdr_ctrl/branches<br />+ /sdr_ctrl/tags<br />+ /sdr_ctrl/trunk<br />
root
Tue, 03 Jan 2012 12:45:02 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=1
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.