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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F& Sat, 03 Jun 2023 00:43:57 +0100 FeedCreator 1.7.2 SDRAM top and core related run file list are added ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29 <div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Sat, 28 Jan 2012 12:43:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29 SDRAM top and SDRAM Core Golden files are added into ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28 <div><strong>Rev 28 - dinesha</strong> (15 file(s) modified)</div><div>SDRAM top and SDRAM Core Golden files are added into ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br /> dinesha Sat, 28 Jan 2012 12:38:25 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28 Golden log file corresponds the SDRAM core level test case ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27 <div><strong>Rev 27 - dinesha</strong> (9 file(s) modified)</div><div>Golden log file corresponds the SDRAM core level test case ...</div>+ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br /> dinesha Fri, 27 Jan 2012 14:33:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27 invalid log files are removed https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=26 <div><strong>Rev 26 - dinesha</strong> (9 file(s) modified)</div><div>invalid log files are removed</div>- /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br /> dinesha Fri, 27 Jan 2012 14:29:44 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=26 tb.sv is renamed as tb_top https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=25 <div><strong>Rev 25 - dinesha</strong> (2 file(s) modified)</div><div>tb.sv is renamed as tb_top</div>- /sdr_ctrl/trunk/verif/tb/tb.sv<br />+ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 27 Jan 2012 14:12:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=25 Clean Up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=24 <div><strong>Rev 24 - dinesha</strong> (1 file(s) modified)</div><div>Clean Up</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Fri, 27 Jan 2012 14:11:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=24 Pad sdram clock added and read path register w.r.t pad ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=23 <div><strong>Rev 23 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added and read path register w.r.t pad ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br /> dinesha Thu, 26 Jan 2012 09:00:10 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=23 Pad sdram clock added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=22 <div><strong>Rev 22 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Thu, 26 Jan 2012 08:57:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=22 Clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=21 <div><strong>Rev 21 - dinesha</strong> (6 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br /> dinesha Thu, 26 Jan 2012 08:53:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=21 8 Bit SDARM support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=20 <div><strong>Rev 20 - dinesha</strong> (9 file(s) modified)</div><div>8 Bit SDARM support is added</div>+ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br /> dinesha Tue, 24 Jan 2012 14:11:45 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=20 8 Bit SDRAM Support added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=19 <div><strong>Rev 19 - dinesha</strong> (2 file(s) modified)</div><div>8 Bit SDRAM Support added</div>~ /sdr_ctrl/trunk/verif/run/filelist.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Tue, 24 Jan 2012 14:09:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=19 8 Bit SDRAM Support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=18 <div><strong>Rev 18 - dinesha</strong> (1 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Tue, 24 Jan 2012 14:07:34 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=18 micron 8 bit memory models are added into svn https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=17 <div><strong>Rev 17 - dinesha</strong> (2 file(s) modified)</div><div>micron 8 bit memory models are added into svn</div>+ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br />+ /sdr_ctrl/trunk/verif/model/mt48lc8m16a2.v<br /> dinesha Tue, 24 Jan 2012 14:01:14 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=17 8 Bit SDRAM Support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=16 <div><strong>Rev 16 - dinesha</strong> (3 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br /> dinesha Tue, 24 Jan 2012 13:57:30 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=16 Port cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=15 <div><strong>Rev 15 - dinesha</strong> (4 file(s) modified)</div><div>Port cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br /> dinesha Sat, 21 Jan 2012 13:16:56 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=15 Unnecessary device config are removed https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=14 <div><strong>Rev 14 - dinesha</strong> (1 file(s) modified)</div><div>Unnecessary device config are removed</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Sat, 21 Jan 2012 13:10:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=14 column bit are made progrmmable https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=13 <div><strong>Rev 13 - dinesha</strong> (3 file(s) modified)</div><div>column bit are made progrmmable</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br /> dinesha Sat, 21 Jan 2012 12:56:43 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=13 Column Bits are made programmable https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=12 <div><strong>Rev 12 - dinesha</strong> (1 file(s) modified)</div><div>Column Bits are made programmable</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Sat, 21 Jan 2012 12:53:26 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=12 SDRAM Specification document added into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=11 <div><strong>Rev 11 - dinesha</strong> (1 file(s) modified)</div><div>SDRAM Specification document added into SVN</div>+ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Wed, 18 Jan 2012 12:02:44 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=11 Waveform files are added into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=10 <div><strong>Rev 10 - dinesha</strong> (6 file(s) modified)</div><div>Waveform files are added into SVN</div>+ /sdr_ctrl/trunk/verif/dump/Application-ReadRequest.jpg<br />+ /sdr_ctrl/trunk/verif/dump/Application-WriteRequest.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-16Bit-Read-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-16Bit-Write-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-32Bit-Read-Transaction.jpg<br />+ /sdr_ctrl/trunk/verif/dump/SDR-32Bit-Write-Transaction.jpg<br /> dinesha Wed, 18 Jan 2012 11:57:17 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=10
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