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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
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sdr_ctrl
WebSVN RSS feed - sdr_ctrl
https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&
Fri, 29 Mar 2024 10:42:59 +0100
FeedCreator 1.7.2
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Port Name clean up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=38
<div><strong>Rev 38 - dinesha</strong> (2 file(s) modified)</div><div>Port Name clean up</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Tue, 31 Jan 2012 06:38:02 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=38
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SDRAM dq and sdram pad clock are termindated inside the ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=37
<div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Tue, 31 Jan 2012 04:53:16 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=37
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Clean up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=36
<div><strong>Rev 36 - dinesha</strong> (1 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />
dinesha
Mon, 30 Jan 2012 14:03:08 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=36
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Updated the New Documents - ver 0.1
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=35
<div><strong>Rev 35 - dinesha</strong> (1 file(s) modified)</div><div>Updated the New Documents - ver 0.1</div>+ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br />
dinesha
Mon, 30 Jan 2012 12:26:17 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=35
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Removed the older version
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=34
<div><strong>Rev 34 - dinesha</strong> (1 file(s) modified)</div><div>Removed the older version</div>- /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br />
dinesha
Mon, 30 Jan 2012 12:23:59 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=34
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clean up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=33
<div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />
dinesha
Mon, 30 Jan 2012 11:54:32 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=33
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Debug is enable through +define
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=32
<div><strong>Rev 32 - dinesha</strong> (1 file(s) modified)</div><div>Debug is enable through +define</div>~ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br />
dinesha
Sat, 28 Jan 2012 12:58:53 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=32
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Integrated SDRAM controller with wishbone interface is added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=31
<div><strong>Rev 31 - dinesha</strong> (8 file(s) modified)</div><div>Integrated SDRAM controller with wishbone interface is added into SVN</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br />+ /sdr_ctrl/trunk/rtl/lib/sync_fifo.v<br />+ /sdr_ctrl/trunk/rtl/top<br />+ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />
dinesha
Sat, 28 Jan 2012 12:56:29 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=31
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test bench file for integrated SDRAM controller with wish bone ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=30
<div><strong>Rev 30 - dinesha</strong> (2 file(s) modified)</div><div>test bench file for integrated SDRAM controller with wish bone ...</div>+ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Sat, 28 Jan 2012 12:46:31 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=30
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SDRAM top and core related run file list are added ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29
<div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />
dinesha
Sat, 28 Jan 2012 12:43:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=29
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SDRAM top and SDRAM Core Golden files are added into ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28
<div><strong>Rev 28 - dinesha</strong> (15 file(s) modified)</div><div>SDRAM top and SDRAM Core Golden files are added into ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br />
dinesha
Sat, 28 Jan 2012 12:38:25 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=28
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Golden log file corresponds the SDRAM core level test case ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27
<div><strong>Rev 27 - dinesha</strong> (9 file(s) modified)</div><div>Golden log file corresponds the SDRAM core level test case ...</div>+ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br />
dinesha
Fri, 27 Jan 2012 14:33:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=27
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invalid log files are removed
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=26
<div><strong>Rev 26 - dinesha</strong> (9 file(s) modified)</div><div>invalid log files are removed</div>- /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Fri, 27 Jan 2012 14:29:44 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=26
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tb.sv is renamed as tb_top
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=25
<div><strong>Rev 25 - dinesha</strong> (2 file(s) modified)</div><div>tb.sv is renamed as tb_top</div>- /sdr_ctrl/trunk/verif/tb/tb.sv<br />+ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Fri, 27 Jan 2012 14:12:33 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=25
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Clean Up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=24
<div><strong>Rev 24 - dinesha</strong> (1 file(s) modified)</div><div>Clean Up</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Fri, 27 Jan 2012 14:11:32 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=24
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Pad sdram clock added and read path register w.r.t pad ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=23
<div><strong>Rev 23 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added and read path register w.r.t pad ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Thu, 26 Jan 2012 09:00:10 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=23
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Pad sdram clock added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=22
<div><strong>Rev 22 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Thu, 26 Jan 2012 08:57:16 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=22
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Clean up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=21
<div><strong>Rev 21 - dinesha</strong> (6 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />
dinesha
Thu, 26 Jan 2012 08:53:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=21
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8 Bit SDARM support is added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=20
<div><strong>Rev 20 - dinesha</strong> (9 file(s) modified)</div><div>8 Bit SDARM support is added</div>+ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Tue, 24 Jan 2012 14:11:45 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=20
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8 Bit SDRAM Support added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=19
<div><strong>Rev 19 - dinesha</strong> (2 file(s) modified)</div><div>8 Bit SDRAM Support added</div>~ /sdr_ctrl/trunk/verif/run/filelist.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />
dinesha
Tue, 24 Jan 2012 14:09:33 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=19
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