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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F& Tue, 07 Feb 2023 02:22:22 +0100 FeedCreator 1.7.2 SDRAM Address bit increased from 12 bit to 13 bit https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=68 <div><strong>Rev 68 - dinesha</strong> (2 file(s) modified)</div><div>SDRAM Address bit increased from 12 bit to 13 bit</div>~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 26 Apr 2013 11:31:25 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=68 time scale removed https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=67 <div><strong>Rev 67 - dinesha</strong> (3 file(s) modified)</div><div>time scale removed</div>+ /sdr_ctrl/trunk/fpga<br />+ /sdr_ctrl/trunk/fpga/actel<br />~ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br /> dinesha Fri, 15 Feb 2013 13:04:35 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=67 dwm tw, bl paramter are passed on the wb2sdrc module https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=66 <div><strong>Rev 66 - dinesha</strong> (1 file(s) modified)</div><div>dwm tw, bl paramter are passed on the wb2sdrc module</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Tue, 12 Jun 2012 12:19:42 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=66 Updated Log file with CAS latency support 4,5 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=65 <div><strong>Rev 65 - dinesha</strong> (15 file(s) modified)</div><div>Updated Log file with CAS latency support 4,5</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br /> dinesha Tue, 12 Jun 2012 04:35:04 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=65 CAS Latency support added for 4,5 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=64 <div><strong>Rev 64 - dinesha</strong> (1 file(s) modified)</div><div>CAS Latency support added for 4,5</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Tue, 12 Jun 2012 04:33:02 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=64 FPGA Bench mark results are added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=63 <div><strong>Rev 63 - dinesha</strong> (1 file(s) modified)</div><div>FPGA Bench mark results are added</div>~ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Tue, 14 Feb 2012 05:35:06 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=63 Synthesis constraint for simplify https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=62 <div><strong>Rev 62 - dinesha</strong> (1 file(s) modified)</div><div>Synthesis constraint for simplify</div>+ /sdr_ctrl/trunk/synth/constraints/sdrc_top.sdc<br /> dinesha Tue, 14 Feb 2012 05:18:36 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=62 RTL file list are added into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=61 <div><strong>Rev 61 - dinesha</strong> (1 file(s) modified)</div><div>RTL file list are added into SVN</div>+ /sdr_ctrl/trunk/rtl/filelist_rtl.f<br /> dinesha Tue, 14 Feb 2012 04:37:47 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=61 warning cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=60 <div><strong>Rev 60 - dinesha</strong> (1 file(s) modified)</div><div>warning cleanup</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Tue, 14 Feb 2012 04:34:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=60 Control path request and data are register now for better ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=59 <div><strong>Rev 59 - dinesha</strong> (1 file(s) modified)</div><div>Control path request and data are register now for better ...</div>~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Tue, 14 Feb 2012 04:32:45 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=59 Read Data is register on RD_FAST=0 case https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=58 <div><strong>Rev 58 - dinesha</strong> (1 file(s) modified)</div><div>Read Data is register on RD_FAST=0 case</div>~ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br /> dinesha Tue, 14 Feb 2012 04:30:57 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=58 Synthesis constraints are added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=57 <div><strong>Rev 57 - dinesha</strong> (3 file(s) modified)</div><div>Synthesis constraints are added</div>+ /sdr_ctrl/trunk/synth<br />+ /sdr_ctrl/trunk/synth/constraints<br />+ /sdr_ctrl/trunk/synth/constraints/sdrc_synth.sdc<br /> dinesha Mon, 13 Feb 2012 13:59:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=57 FPGA Synth optimisation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=56 <div><strong>Rev 56 - dinesha</strong> (14 file(s) modified)</div><div>FPGA Synth optimisation</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Mon, 13 Feb 2012 12:53:19 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=56 FPGA Synthesis timing optimisation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=55 <div><strong>Rev 55 - dinesha</strong> (7 file(s) modified)</div><div>FPGA Synthesis timing optimisation</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Mon, 13 Feb 2012 12:41:47 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=55 FPGA Timing Optimisation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=54 <div><strong>Rev 54 - dinesha</strong> (6 file(s) modified)</div><div>FPGA Timing Optimisation</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Fri, 10 Feb 2012 14:55:05 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=54 Test bench upgradation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=53 <div><strong>Rev 53 - dinesha</strong> (14 file(s) modified)</div><div>Test bench upgradation</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 09 Feb 2012 14:41:41 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=53 Documentation update for request control and transfer control block https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=52 <div><strong>Rev 52 - dinesha</strong> (1 file(s) modified)</div><div>Documentation update for request control and transfer control block</div>~ /sdr_ctrl/trunk/doc/sdram_controller_specs.pdf<br /> dinesha Thu, 09 Feb 2012 14:36:02 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=52 FPGA relating timing optimisation done https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=51 <div><strong>Rev 51 - dinesha</strong> (6 file(s) modified)</div><div>FPGA relating timing optimisation done</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Thu, 09 Feb 2012 14:15:25 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=51 Bug fix the request length is fixe https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=50 <div><strong>Rev 50 - dinesha</strong> (6 file(s) modified)</div><div>Bug fix the request length is fixe</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Tue, 07 Feb 2012 10:25:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=50 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=49 <div><strong>Rev 49 - dinesha</strong> (7 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br /> dinesha Mon, 06 Feb 2012 11:33:51 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2F&rev=49
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