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sdr_ctrl
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https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&
Fri, 29 Mar 2024 14:35:41 +0100
FeedCreator 1.7.2
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Pad sdram clock added and read path register w.r.t pad ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=23
<div><strong>Rev 23 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added and read path register w.r.t pad ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Thu, 26 Jan 2012 09:00:10 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=23
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8 Bit SDRAM Support is added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=16
<div><strong>Rev 16 - dinesha</strong> (3 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />
dinesha
Tue, 24 Jan 2012 13:57:30 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=16
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Port cleanup
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=15
<div><strong>Rev 15 - dinesha</strong> (4 file(s) modified)</div><div>Port cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />
dinesha
Sat, 21 Jan 2012 13:16:56 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=15
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column bit are made progrmmable
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=13
<div><strong>Rev 13 - dinesha</strong> (3 file(s) modified)</div><div>column bit are made progrmmable</div>~ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />
dinesha
Sat, 21 Jan 2012 12:56:43 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=13
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SDR Bus width parameter passing issue across the models are ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=9
<div><strong>Rev 9 - dinesha</strong> (1 file(s) modified)</div><div>SDR Bus width parameter passing issue across the models are ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Tue, 17 Jan 2012 12:13:44 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=9
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Sdram controller RTL bug fixes done for 16bit SDR Mode
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=4
<div><strong>Rev 4 - dinesha</strong> (4 file(s) modified)</div><div>Sdram controller RTL bug fixes done for 16bit SDR Mode</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />
dinesha
Mon, 16 Jan 2012 14:54:21 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=4
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SDRAM controller core files are checked in
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=3
<div><strong>Rev 3 - dinesha</strong> (7 file(s) modified)</div><div>SDRAM controller core files are checked in</div>+ /sdr_ctrl/trunk/rtl/core<br />+ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />
dinesha
Tue, 10 Jan 2012 04:39:31 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=3
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...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=2
<div><strong>Rev 2 - dinesha</strong> (16 file(s) modified)</div><div>...</div>+ /sdr_ctrl/trunk/doc<br />+ /sdr_ctrl/trunk/env<br />+ /sdr_ctrl/trunk/models<br />+ /sdr_ctrl/trunk/rtl<br />+ /sdr_ctrl/trunk/rtl/defs<br />+ /sdr_ctrl/trunk/rtl/lib<br />+ /sdr_ctrl/trunk/verif<br />+ /sdr_ctrl/trunk/verif/agents<br />+ /sdr_ctrl/trunk/verif/defs<br />+ /sdr_ctrl/trunk/verif/dump<br />+ /sdr_ctrl/trunk/verif/lib<br />+ /sdr_ctrl/trunk/verif/log<br />+ /sdr_ctrl/trunk/verif/model<br />+ /sdr_ctrl/trunk/verif/run<br />+ /sdr_ctrl/trunk/verif/tb<br />+ /sdr_ctrl/trunk/verif/test_case<br />
dinesha
Sat, 07 Jan 2012 12:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2F&rev=2
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