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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2Fsdrc_bs_convert.v& Mon, 25 Sep 2023 19:13:36 +0100 FeedCreator 1.7.2 SDRAM dq and sdram pad clock are termindated inside the ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=37 <div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 04:53:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=37 Integrated SDRAM controller with wishbone interface is added into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=31 <div><strong>Rev 31 - dinesha</strong> (8 file(s) modified)</div><div>Integrated SDRAM controller with wishbone interface is added into SVN</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br />+ /sdr_ctrl/trunk/rtl/lib/sync_fifo.v<br />+ /sdr_ctrl/trunk/rtl/top<br />+ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Sat, 28 Jan 2012 12:56:29 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=31 8 Bit SDRAM Support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=16 <div><strong>Rev 16 - dinesha</strong> (3 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br /> dinesha Tue, 24 Jan 2012 13:57:30 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=16 Sdram controller RTL bug fixes done for 16bit SDR Mode https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=4 <div><strong>Rev 4 - dinesha</strong> (4 file(s) modified)</div><div>Sdram controller RTL bug fixes done for 16bit SDR Mode</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br /> dinesha Mon, 16 Jan 2012 14:54:21 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=4 SDRAM controller core files are checked in https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=3 <div><strong>Rev 3 - dinesha</strong> (7 file(s) modified)</div><div>SDRAM controller core files are checked in</div>+ /sdr_ctrl/trunk/rtl/core<br />+ /sdr_ctrl/trunk/rtl/core/sdrc.def<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br /> dinesha Tue, 10 Jan 2012 04:39:31 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Fcore%2F&rev=3
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