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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F& Tue, 21 May 2024 13:02:50 +0100 FeedCreator 1.7.2 Warning cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=71 <div><strong>Rev 71 - dinesha</strong> (2 file(s) modified)</div><div>Warning cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Fri, 26 Apr 2013 12:37:45 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=71 SDRAM address bit increased from 12 bit to 13 bit https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=69 <div><strong>Rev 69 - dinesha</strong> (7 file(s) modified)</div><div>SDRAM address bit increased from 12 bit to 13 bit</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Fri, 26 Apr 2013 11:31:59 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=69 dwm tw, bl paramter are passed on the wb2sdrc module https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=66 <div><strong>Rev 66 - dinesha</strong> (1 file(s) modified)</div><div>dwm tw, bl paramter are passed on the wb2sdrc module</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Tue, 12 Jun 2012 12:19:42 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=66 warning cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=60 <div><strong>Rev 60 - dinesha</strong> (1 file(s) modified)</div><div>warning cleanup</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Tue, 14 Feb 2012 04:34:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=60 FPGA Synthesis timing optimisation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=55 <div><strong>Rev 55 - dinesha</strong> (7 file(s) modified)</div><div>FPGA Synthesis timing optimisation</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Mon, 13 Feb 2012 12:41:47 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=55 SDRAM bus converter bug fix and top-level signal clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=47 <div><strong>Rev 47 - dinesha</strong> (4 file(s) modified)</div><div>SDRAM bus converter bug fix and top-level signal clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br /> dinesha Mon, 06 Feb 2012 11:17:43 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=47 test bench upgrade + rtl cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=46 <div><strong>Rev 46 - dinesha</strong> (17 file(s) modified)</div><div>test bench upgrade + rtl cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 10:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=46 Port Name clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=38 <div><strong>Rev 38 - dinesha</strong> (2 file(s) modified)</div><div>Port Name clean up</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 06:38:02 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=38 SDRAM dq and sdram pad clock are termindated inside the ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=37 <div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 04:53:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=37 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=33 <div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Mon, 30 Jan 2012 11:54:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=33 Integrated SDRAM controller with wishbone interface is added into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=31 <div><strong>Rev 31 - dinesha</strong> (8 file(s) modified)</div><div>Integrated SDRAM controller with wishbone interface is added into SVN</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/lib/async_fifo.v<br />+ /sdr_ctrl/trunk/rtl/lib/sync_fifo.v<br />+ /sdr_ctrl/trunk/rtl/top<br />+ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc<br />+ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br /> dinesha Sat, 28 Jan 2012 12:56:29 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Frtl%2Ftop%2F&rev=31
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