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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F& Sun, 28 May 2023 17:15:31 +0100 FeedCreator 1.7.2 sdram bug in FPGA mode + 8/16 bit address map ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=73 <div><strong>Rev 73 - dinesha</strong> (11 file(s) modified)</div><div>sdram bug in FPGA mode + 8/16 bit address map ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 27 Aug 2021 13:24:23 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=73 Command Clean up for model-sim mode https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=72 <div><strong>Rev 72 - dinesha</strong> (2 file(s) modified)</div><div>Command Clean up for model-sim mode</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />~ /sdr_ctrl/trunk/verif/run/read.me<br /> dinesha Mon, 17 Jun 2013 04:44:18 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=72 Warning Cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=70 <div><strong>Rev 70 - dinesha</strong> (2 file(s) modified)</div><div>Warning Cleanup</div>~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 26 Apr 2013 12:37:13 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=70 SDRAM Address bit increased from 12 bit to 13 bit https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=68 <div><strong>Rev 68 - dinesha</strong> (2 file(s) modified)</div><div>SDRAM Address bit increased from 12 bit to 13 bit</div>~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 26 Apr 2013 11:31:25 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=68 Updated Log file with CAS latency support 4,5 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=65 <div><strong>Rev 65 - dinesha</strong> (15 file(s) modified)</div><div>Updated Log file with CAS latency support 4,5</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br /> dinesha Tue, 12 Jun 2012 04:35:04 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=65 FPGA Synth optimisation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=56 <div><strong>Rev 56 - dinesha</strong> (14 file(s) modified)</div><div>FPGA Synth optimisation</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Mon, 13 Feb 2012 12:53:19 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=56 Test bench upgradation https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=53 <div><strong>Rev 53 - dinesha</strong> (14 file(s) modified)</div><div>Test bench upgradation</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 09 Feb 2012 14:41:41 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=53 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=49 <div><strong>Rev 49 - dinesha</strong> (7 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br /> dinesha Mon, 06 Feb 2012 11:33:51 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=49 top-level cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=48 <div><strong>Rev 48 - dinesha</strong> (14 file(s) modified)</div><div>top-level cleanup</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Mon, 06 Feb 2012 11:21:45 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=48 test bench upgrade + rtl cleanup https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=46 <div><strong>Rev 46 - dinesha</strong> (17 file(s) modified)</div><div>test bench upgrade + rtl cleanup</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 10:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=46 RTL clean up and logic seperation done from sdram bus ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=45 <div><strong>Rev 45 - dinesha</strong> (19 file(s) modified)</div><div>RTL clean up and logic seperation done from sdram bus ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/read.me<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 06:17:34 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=45 SDRAM data path logic is modified to support 4 command ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=44 <div><strong>Rev 44 - dinesha</strong> (8 file(s) modified)</div><div>SDRAM data path logic is modified to support 4 command ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 08:12:21 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=44 Test bench automation to handle differ write/read burst sequence is ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=43 <div><strong>Rev 43 - dinesha</strong> (15 file(s) modified)</div><div>Test bench automation to handle differ write/read burst sequence is ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 06:27:19 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=43 Test Bench upgradation with bigger data burst size https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=39 <div><strong>Rev 39 - dinesha</strong> (7 file(s) modified)</div><div>Test Bench upgradation with bigger data burst size</div>~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Wed, 01 Feb 2012 11:39:09 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=39 Port Name clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=38 <div><strong>Rev 38 - dinesha</strong> (2 file(s) modified)</div><div>Port Name clean up</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 06:38:02 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=38 SDRAM dq and sdram pad clock are termindated inside the ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=37 <div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 04:53:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=37 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=33 <div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Mon, 30 Jan 2012 11:54:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=33 Debug is enable through +define https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=32 <div><strong>Rev 32 - dinesha</strong> (1 file(s) modified)</div><div>Debug is enable through +define</div>~ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br /> dinesha Sat, 28 Jan 2012 12:58:53 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=32 test bench file for integrated SDRAM controller with wish bone ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=30 <div><strong>Rev 30 - dinesha</strong> (2 file(s) modified)</div><div>test bench file for integrated SDRAM controller with wish bone ...</div>+ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 28 Jan 2012 12:46:31 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=30 SDRAM top and core related run file list are added ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=29 <div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Sat, 28 Jan 2012 12:43:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=29
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