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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F& Mon, 10 Aug 2026 13:55:28 +0100 FeedCreator 1.7.2 SDRAM data path logic is modified to support 4 command ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=44 <div><strong>Rev 44 - dinesha</strong> (8 file(s) modified)</div><div>SDRAM data path logic is modified to support 4 command ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 08:12:21 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=44 Test bench automation to handle differ write/read burst sequence is ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=43 <div><strong>Rev 43 - dinesha</strong> (15 file(s) modified)</div><div>Test bench automation to handle differ write/read burst sequence is ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 06:27:19 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=43 Test Bench upgradation with bigger data burst size https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=39 <div><strong>Rev 39 - dinesha</strong> (7 file(s) modified)</div><div>Test Bench upgradation with bigger data burst size</div>~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Wed, 01 Feb 2012 11:39:09 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=39 Port Name clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=38 <div><strong>Rev 38 - dinesha</strong> (2 file(s) modified)</div><div>Port Name clean up</div>~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 06:38:02 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=38 SDRAM dq and sdram pad clock are termindated inside the ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=37 <div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Tue, 31 Jan 2012 04:53:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=37 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=33 <div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Mon, 30 Jan 2012 11:54:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=33 Debug is enable through +define https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=32 <div><strong>Rev 32 - dinesha</strong> (1 file(s) modified)</div><div>Debug is enable through +define</div>~ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br /> dinesha Sat, 28 Jan 2012 12:58:53 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=32 test bench file for integrated SDRAM controller with wish bone ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=30 <div><strong>Rev 30 - dinesha</strong> (2 file(s) modified)</div><div>test bench file for integrated SDRAM controller with wish bone ...</div>+ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 28 Jan 2012 12:46:31 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=30 SDRAM top and core related run file list are added ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=29 <div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Sat, 28 Jan 2012 12:43:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=29 SDRAM top and SDRAM Core Golden files are added into ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=28 <div><strong>Rev 28 - dinesha</strong> (15 file(s) modified)</div><div>SDRAM top and SDRAM Core Golden files are added into ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br /> dinesha Sat, 28 Jan 2012 12:38:25 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=28 Golden log file corresponds the SDRAM core level test case ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=27 <div><strong>Rev 27 - dinesha</strong> (9 file(s) modified)</div><div>Golden log file corresponds the SDRAM core level test case ...</div>+ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br /> dinesha Fri, 27 Jan 2012 14:33:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=27 invalid log files are removed https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=26 <div><strong>Rev 26 - dinesha</strong> (9 file(s) modified)</div><div>invalid log files are removed</div>- /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br /> dinesha Fri, 27 Jan 2012 14:29:44 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=26 tb.sv is renamed as tb_top https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=25 <div><strong>Rev 25 - dinesha</strong> (2 file(s) modified)</div><div>tb.sv is renamed as tb_top</div>- /sdr_ctrl/trunk/verif/tb/tb.sv<br />+ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Fri, 27 Jan 2012 14:12:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=25 Clean Up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=24 <div><strong>Rev 24 - dinesha</strong> (1 file(s) modified)</div><div>Clean Up</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Fri, 27 Jan 2012 14:11:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=24 Pad sdram clock added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=22 <div><strong>Rev 22 - dinesha</strong> (1 file(s) modified)</div><div>Pad sdram clock added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Thu, 26 Jan 2012 08:57:16 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=22 Clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=21 <div><strong>Rev 21 - dinesha</strong> (6 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br /> dinesha Thu, 26 Jan 2012 08:53:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=21 8 Bit SDARM support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=20 <div><strong>Rev 20 - dinesha</strong> (9 file(s) modified)</div><div>8 Bit SDARM support is added</div>+ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br /> dinesha Tue, 24 Jan 2012 14:11:45 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=20 8 Bit SDRAM Support added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=19 <div><strong>Rev 19 - dinesha</strong> (2 file(s) modified)</div><div>8 Bit SDRAM Support added</div>~ /sdr_ctrl/trunk/verif/run/filelist.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Tue, 24 Jan 2012 14:09:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=19 8 Bit SDRAM Support is added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=18 <div><strong>Rev 18 - dinesha</strong> (1 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br /> dinesha Tue, 24 Jan 2012 14:07:34 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=18 micron 8 bit memory models are added into svn https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=17 <div><strong>Rev 17 - dinesha</strong> (2 file(s) modified)</div><div>micron 8 bit memory models are added into svn</div>+ /sdr_ctrl/trunk/verif/model/mt48lc8m8a2.v<br />+ /sdr_ctrl/trunk/verif/model/mt48lc8m16a2.v<br /> dinesha Tue, 24 Jan 2012 14:01:14 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2F&rev=17

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