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sdr_ctrl
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https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&
Fri, 29 Mar 2024 12:46:36 +0100
FeedCreator 1.7.2
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SDRAM data path logic is modified to support 4 command ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=44
<div><strong>Rev 44 - dinesha</strong> (8 file(s) modified)</div><div>SDRAM data path logic is modified to support 4 command ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Thu, 02 Feb 2012 08:12:21 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=44
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Test bench automation to handle differ write/read burst sequence is ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=43
<div><strong>Rev 43 - dinesha</strong> (15 file(s) modified)</div><div>Test bench automation to handle differ write/read burst sequence is ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Thu, 02 Feb 2012 06:27:19 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=43
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Test Bench upgradation with bigger data burst size
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=39
<div><strong>Rev 39 - dinesha</strong> (7 file(s) modified)</div><div>Test Bench upgradation with bigger data burst size</div>~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Wed, 01 Feb 2012 11:39:09 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=39
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SDRAM dq and sdram pad clock are termindated inside the ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=37
<div><strong>Rev 37 - dinesha</strong> (17 file(s) modified)</div><div>SDRAM dq and sdram pad clock are termindated inside the ...</div>- /sdr_ctrl/trunk/rtl/core/sdrc.def<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_ctl.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bank_fsm.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />+ /sdr_ctrl/trunk/rtl/core/sdrc_define.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br />
dinesha
Tue, 31 Jan 2012 04:53:16 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=37
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SDRAM top and SDRAM Core Golden files are added into ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=28
<div><strong>Rev 28 - dinesha</strong> (15 file(s) modified)</div><div>SDRAM top and SDRAM Core Golden files are added into ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_complie.log<br />
dinesha
Sat, 28 Jan 2012 12:38:25 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=28
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Golden log file corresponds the SDRAM core level test case ...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=27
<div><strong>Rev 27 - dinesha</strong> (9 file(s) modified)</div><div>Golden log file corresponds the SDRAM core level test case ...</div>+ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_complie.log<br />
dinesha
Fri, 27 Jan 2012 14:33:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=27
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invalid log files are removed
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=26
<div><strong>Rev 26 - dinesha</strong> (9 file(s) modified)</div><div>invalid log files are removed</div>- /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />- /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />- /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Fri, 27 Jan 2012 14:29:44 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=26
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Clean up
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=21
<div><strong>Rev 21 - dinesha</strong> (6 file(s) modified)</div><div>Clean up</div>~ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />
dinesha
Thu, 26 Jan 2012 08:53:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=21
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8 Bit SDARM support is added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=20
<div><strong>Rev 20 - dinesha</strong> (9 file(s) modified)</div><div>8 Bit SDARM support is added</div>+ /sdr_ctrl/trunk/verif/log/sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_8BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Tue, 24 Jan 2012 14:11:45 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=20
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Golden Log files are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=6
<div><strong>Rev 6 - dinesha</strong> (6 file(s) modified)</div><div>Golden Log files are added into SVN</div>+ /sdr_ctrl/trunk/verif/log/sdr16_sim.log<br />+ /sdr_ctrl/trunk/verif/log/sdr32_sim.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_16BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_16BIT_complie.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_32BIT_basic_test1.log<br />+ /sdr_ctrl/trunk/verif/log/SDR_32BIT_complie.log<br />
dinesha
Tue, 17 Jan 2012 12:00:29 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=6
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...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=2
<div><strong>Rev 2 - dinesha</strong> (16 file(s) modified)</div><div>...</div>+ /sdr_ctrl/trunk/doc<br />+ /sdr_ctrl/trunk/env<br />+ /sdr_ctrl/trunk/models<br />+ /sdr_ctrl/trunk/rtl<br />+ /sdr_ctrl/trunk/rtl/defs<br />+ /sdr_ctrl/trunk/rtl/lib<br />+ /sdr_ctrl/trunk/verif<br />+ /sdr_ctrl/trunk/verif/agents<br />+ /sdr_ctrl/trunk/verif/defs<br />+ /sdr_ctrl/trunk/verif/dump<br />+ /sdr_ctrl/trunk/verif/lib<br />+ /sdr_ctrl/trunk/verif/log<br />+ /sdr_ctrl/trunk/verif/model<br />+ /sdr_ctrl/trunk/verif/run<br />+ /sdr_ctrl/trunk/verif/tb<br />+ /sdr_ctrl/trunk/verif/test_case<br />
dinesha
Sat, 07 Jan 2012 12:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Flog%2F&rev=2
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