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sdr_ctrl WebSVN RSS feed - sdr_ctrl https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F& Sun, 04 Jun 2023 00:53:26 +0100 FeedCreator 1.7.2 Command Clean up for model-sim mode https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=72 <div><strong>Rev 72 - dinesha</strong> (2 file(s) modified)</div><div>Command Clean up for model-sim mode</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />~ /sdr_ctrl/trunk/verif/run/read.me<br /> dinesha Mon, 17 Jun 2013 04:44:18 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=72 RTL clean up and logic seperation done from sdram bus ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=45 <div><strong>Rev 45 - dinesha</strong> (19 file(s) modified)</div><div>RTL clean up and logic seperation done from sdram bus ...</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_bs_convert.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_xfr_ctl.v<br />~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/read.me<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Sat, 04 Feb 2012 06:17:34 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=45 Test bench automation to handle differ write/read burst sequence is ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=43 <div><strong>Rev 43 - dinesha</strong> (15 file(s) modified)</div><div>Test bench automation to handle differ write/read burst sequence is ...</div>~ /sdr_ctrl/trunk/verif/log/core_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr8_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr16_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_sdr32_sim.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br />~ /sdr_ctrl/trunk/verif/tb/tb_core.sv<br />~ /sdr_ctrl/trunk/verif/tb/tb_top.sv<br /> dinesha Thu, 02 Feb 2012 06:27:19 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=43 clean up https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=33 <div><strong>Rev 33 - dinesha</strong> (6 file(s) modified)</div><div>clean up</div>~ /sdr_ctrl/trunk/rtl/core/sdrc_core.v<br />~ /sdr_ctrl/trunk/rtl/core/sdrc_req_gen.v<br />~ /sdr_ctrl/trunk/rtl/top/sdrc_top.v<br />~ /sdr_ctrl/trunk/rtl/wb2sdrc/wb2sdrc.v<br />+ /sdr_ctrl/trunk/verif/run/regression_analysis<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Mon, 30 Jan 2012 11:54:32 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=33 SDRAM top and core related run file list are added ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=29 <div><strong>Rev 29 - dinesha</strong> (6 file(s) modified)</div><div>SDRAM top and core related run file list are added ...</div>~ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist_core.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_rtl.f<br />+ /sdr_ctrl/trunk/verif/run/filelist_top.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br />~ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Sat, 28 Jan 2012 12:43:55 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=29 8 Bit SDRAM Support added https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=19 <div><strong>Rev 19 - dinesha</strong> (2 file(s) modified)</div><div>8 Bit SDRAM Support added</div>~ /sdr_ctrl/trunk/verif/run/filelist.f<br />~ /sdr_ctrl/trunk/verif/run/run_all<br /> dinesha Tue, 24 Jan 2012 14:09:33 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=19 Run files are updated into SVN https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=5 <div><strong>Rev 5 - dinesha</strong> (6 file(s) modified)</div><div>Run files are updated into SVN</div>+ /sdr_ctrl/trunk/verif/run/compile.modelsim<br />+ /sdr_ctrl/trunk/verif/run/filelist.f<br />+ /sdr_ctrl/trunk/verif/run/read.me<br />+ /sdr_ctrl/trunk/verif/run/run.do<br />+ /sdr_ctrl/trunk/verif/run/run_all<br />+ /sdr_ctrl/trunk/verif/run/run_modelsim<br /> dinesha Tue, 17 Jan 2012 11:59:49 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=5 ... https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=2 <div><strong>Rev 2 - dinesha</strong> (16 file(s) modified)</div><div>...</div>+ /sdr_ctrl/trunk/doc<br />+ /sdr_ctrl/trunk/env<br />+ /sdr_ctrl/trunk/models<br />+ /sdr_ctrl/trunk/rtl<br />+ /sdr_ctrl/trunk/rtl/defs<br />+ /sdr_ctrl/trunk/rtl/lib<br />+ /sdr_ctrl/trunk/verif<br />+ /sdr_ctrl/trunk/verif/agents<br />+ /sdr_ctrl/trunk/verif/defs<br />+ /sdr_ctrl/trunk/verif/dump<br />+ /sdr_ctrl/trunk/verif/lib<br />+ /sdr_ctrl/trunk/verif/log<br />+ /sdr_ctrl/trunk/verif/model<br />+ /sdr_ctrl/trunk/verif/run<br />+ /sdr_ctrl/trunk/verif/tb<br />+ /sdr_ctrl/trunk/verif/test_case<br /> dinesha Sat, 07 Jan 2012 12:33:38 +0100 https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Frun%2F&rev=2
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