URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Error creating feed file, please check write permissions.
sdr_ctrl
WebSVN RSS feed - sdr_ctrl
https://opencores.org/websvn//websvn/listing?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&
Fri, 29 Mar 2024 00:12:08 +0100
FeedCreator 1.7.2
-
8 Bit SDRAM Support is added
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=18
<div><strong>Rev 18 - dinesha</strong> (1 file(s) modified)</div><div>8 Bit SDRAM Support is added</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Tue, 24 Jan 2012 14:07:34 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=18
-
Unnecessary device config are removed
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=14
<div><strong>Rev 14 - dinesha</strong> (1 file(s) modified)</div><div>Unnecessary device config are removed</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Sat, 21 Jan 2012 13:10:33 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=14
-
Column Bits are made programmable
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=12
<div><strong>Rev 12 - dinesha</strong> (1 file(s) modified)</div><div>Column Bits are made programmable</div>~ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Sat, 21 Jan 2012 12:53:26 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=12
-
test bench files are added into SVN
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=8
<div><strong>Rev 8 - dinesha</strong> (1 file(s) modified)</div><div>test bench files are added into SVN</div>+ /sdr_ctrl/trunk/verif/tb/tb.sv<br />
dinesha
Tue, 17 Jan 2012 12:11:55 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=8
-
...
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=2
<div><strong>Rev 2 - dinesha</strong> (16 file(s) modified)</div><div>...</div>+ /sdr_ctrl/trunk/doc<br />+ /sdr_ctrl/trunk/env<br />+ /sdr_ctrl/trunk/models<br />+ /sdr_ctrl/trunk/rtl<br />+ /sdr_ctrl/trunk/rtl/defs<br />+ /sdr_ctrl/trunk/rtl/lib<br />+ /sdr_ctrl/trunk/verif<br />+ /sdr_ctrl/trunk/verif/agents<br />+ /sdr_ctrl/trunk/verif/defs<br />+ /sdr_ctrl/trunk/verif/dump<br />+ /sdr_ctrl/trunk/verif/lib<br />+ /sdr_ctrl/trunk/verif/log<br />+ /sdr_ctrl/trunk/verif/model<br />+ /sdr_ctrl/trunk/verif/run<br />+ /sdr_ctrl/trunk/verif/tb<br />+ /sdr_ctrl/trunk/verif/test_case<br />
dinesha
Sat, 07 Jan 2012 12:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=sdr_ctrl&path=%2Fsdr_ctrl%2Ftrunk%2Fverif%2Ftb%2F&rev=2
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.