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spi WebSVN RSS feed - spi https://opencores.org/websvn//websvn/listing?repname=spi&path=%2Fspi%2Ftrunk%2F& Fri, 08 Dec 2023 16:24:52 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Fspi%2Ftrunk%2F&rev=27 <div><strong>Rev 27 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /spi<br />+ /spi/branches<br />+ /spi/tags<br />+ /spi/trunk<br />+ /spi/web_uploads<br />- /tags<br />- /trunk<br /> root Tue, 10 Mar 2009 09:30:47 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Fspi%2Ftrunk%2F&rev=27 CTRL register bit fields changed, VATS testing support added. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=25 <div><strong>Rev 25 - simons</strong> (10 file(s) modified)</div><div>CTRL register bit fields changed, VATS testing support added.</div>~ /trunk/bench/verilog/tb_spi_top.v<br />~ /trunk/doc/spi.pdf<br />~ /trunk/doc/src/spi.doc<br />~ /trunk/rtl/verilog/spi_defines.v<br />+ /trunk/sim/rtl_sim<br />+ /trunk/sim/rtl_sim/run<br />+ /trunk/sim/rtl_sim/run/rtl.fl<br />+ /trunk/sim/rtl_sim/run/run_sim<br />+ /trunk/sim/rtl_sim/run/sim.fl<br />- /trunk/sim/run<br /> simons Mon, 15 Mar 2004 17:46:09 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=25 Byte selects changed. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=21 <div><strong>Rev 21 - simons</strong> (2 file(s) modified)</div><div>Byte selects changed.</div>~ /trunk/rtl/verilog/spi_shift.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Tue, 08 Jul 2003 15:36:37 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=21 Errors fixed. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=19 <div><strong>Rev 19 - simons</strong> (1 file(s) modified)</div><div>Errors fixed.</div>~ /trunk/rtl/verilog/spi_shift.v<br /> simons Mon, 07 Jul 2003 11:26:29 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=19 Define mess fixed. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=17 <div><strong>Rev 17 - simons</strong> (1 file(s) modified)</div><div>Define mess fixed.</div>~ /trunk/rtl/verilog/spi_defines.v<br /> simons Fri, 04 Jul 2003 14:32:51 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=17 Defines set in order. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=15 <div><strong>Rev 15 - simons</strong> (3 file(s) modified)</div><div>Defines set in order.</div>~ /trunk/rtl/verilog/spi_defines.v<br />~ /trunk/rtl/verilog/spi_shift.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Fri, 04 Jul 2003 10:45:11 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=15 8-bit WB access enabled. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=13 <div><strong>Rev 13 - simons</strong> (4 file(s) modified)</div><div>8-bit WB access enabled.</div>~ /trunk/rtl/verilog/spi_clgen.v<br />~ /trunk/rtl/verilog/spi_defines.v<br />~ /trunk/rtl/verilog/spi_shift.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Thu, 03 Jul 2003 17:32:15 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=13 Error fixed. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=12 <div><strong>Rev 12 - simons</strong> (1 file(s) modified)</div><div>Error fixed.</div>~ /trunk/bench/verilog/tb_spi_top.v<br /> simons Fri, 13 Jun 2003 10:07:47 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=12 Slave select signal generation bug fixed, default case added when ... https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=10 <div><strong>Rev 10 - simons</strong> (1 file(s) modified)</div><div>Slave select signal generation bug fixed, default case added when ...</div>~ /trunk/rtl/verilog/spi_top.v<br /> simons Mon, 26 May 2003 10:56:27 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=10 Support for 128 bits character length added. Zero value divider ... https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=9 <div><strong>Rev 9 - simons</strong> (7 file(s) modified)</div><div>Support for 128 bits character length added. Zero value divider ...</div>~ /trunk/bench/verilog/tb_spi_top.v<br />~ /trunk/doc/spi.pdf<br />~ /trunk/doc/src/spi.doc<br />~ /trunk/rtl/verilog/spi_clgen.v<br />~ /trunk/rtl/verilog/spi_defines.v<br />~ /trunk/rtl/verilog/spi_shift.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Tue, 15 Apr 2003 17:11:54 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=9 Automatic slave select signal generation added. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=8 <div><strong>Rev 8 - simons</strong> (6 file(s) modified)</div><div>Automatic slave select signal generation added.</div>~ /trunk/bench/verilog/spi_slave_model.v<br />~ /trunk/bench/verilog/tb_spi_top.v<br />~ /trunk/doc/spi.pdf<br />~ /trunk/doc/src/spi.doc<br />~ /trunk/rtl/verilog/spi_defines.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Wed, 26 Mar 2003 16:00:16 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=8 Support for 64 bit caharacter len added. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=7 <div><strong>Rev 7 - simons</strong> (5 file(s) modified)</div><div>Support for 64 bit caharacter len added.</div>~ /trunk/bench/verilog/tb_spi_top.v<br />~ /trunk/doc/src/spi.doc<br />~ /trunk/rtl/verilog/spi_defines.v<br />~ /trunk/rtl/verilog/spi_shift.v<br />~ /trunk/rtl/verilog/spi_top.v<br /> simons Sat, 28 Dec 2002 03:41:56 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=7 Document lectured. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=5 <div><strong>Rev 5 - simons</strong> (2 file(s) modified)</div><div>Document lectured.</div>~ /trunk/doc/spi.pdf<br />~ /trunk/doc/src/spi.doc<br /> simons Sat, 13 Jul 2002 00:43:21 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=5 PDF created. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=4 <div><strong>Rev 4 - simons</strong> (2 file(s) modified)</div><div>PDF created.</div>+ /trunk/doc/spi.pdf<br />~ /trunk/doc/src/spi.doc<br /> simons Thu, 13 Jun 2002 10:02:52 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=4 Initial import https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=2 <div><strong>Rev 2 - simons</strong> (19 file(s) modified)</div><div>Initial import</div>+ /trunk/bench<br />+ /trunk/bench/verilog<br />+ /trunk/bench/verilog/spi_slave_model.v<br />+ /trunk/bench/verilog/tb_spi_top.v<br />+ /trunk/bench/verilog/wb_master_model.v<br />+ /trunk/doc<br />+ /trunk/doc/src<br />+ /trunk/doc/src/spi.doc<br />+ /trunk/rtl<br />+ /trunk/rtl/verilog<br />+ /trunk/rtl/verilog/spi_clgen.v<br />+ /trunk/rtl/verilog/spi_defines.v<br />+ /trunk/rtl/verilog/spi_shift.v<br />+ /trunk/rtl/verilog/spi_top.v<br />+ /trunk/rtl/verilog/timescale.v<br />+ /trunk/sim<br />+ /trunk/sim/run<br />+ /trunk/sim/run/sim<br />+ /trunk/sim/run/tcl.scr<br /> simons Wed, 12 Jun 2002 15:45:36 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=2 Standard project directories initialized by cvs2svn. https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=1 <div><strong>Rev 1 - </strong> (3 file(s) modified)</div><div>Standard project directories initialized by cvs2svn.</div>+ /branches<br />+ /tags<br />+ /trunk<br /> Wed, 12 Jun 2002 15:45:36 +0100 https://opencores.org/websvn//websvn/revision?repname=spi&path=%2Ftrunk%2F&rev=1
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