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URL https://opencores.org/ocsvn/spislave/spislave/trunk

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spislave WebSVN RSS feed - spislave https://opencores.org/websvn//websvn/listing?repname=spislave&path=%2Fspislave%2F& Sun, 17 May 2026 08:09:30 +0100 FeedCreator 1.7.2 edited copyrghts https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=13 <div><strong>Rev 13 - siva12</strong> (1 file(s) modified)</div><div>edited copyrghts</div>~ /spislave/trunk/spislave/rtl/verilog/spigpio.v<br /> siva12 Sat, 19 Dec 2009 03:44:52 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=13 edited mailid https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=12 <div><strong>Rev 12 - siva12</strong> (1 file(s) modified)</div><div>edited mailid</div>~ /spislave/trunk/spislave/bench/tb_spigpio.v<br /> siva12 Fri, 18 Dec 2009 13:41:24 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=12 edited mailid https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=11 <div><strong>Rev 11 - siva12</strong> (1 file(s) modified)</div><div>edited mailid</div>~ /spislave/trunk/spislave/bench/tb_spigpio.v<br /> siva12 Fri, 18 Dec 2009 13:34:23 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=11 edited mailid https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=10 <div><strong>Rev 10 - siva12</strong> (1 file(s) modified)</div><div>edited mailid</div>~ /spislave/trunk/spislave/rtl/verilog/spigpio.v<br /> siva12 Fri, 18 Dec 2009 13:16:13 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=10 added Makefile https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=9 <div><strong>Rev 9 - siva12</strong> (1 file(s) modified)</div><div>added Makefile</div>~ /spislave/trunk/spislave/bench/Makefile<br /> siva12 Wed, 16 Dec 2009 12:41:26 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=9 added Makefile https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=8 <div><strong>Rev 8 - siva12</strong> (1 file(s) modified)</div><div>added Makefile</div>+ /spislave/trunk/spislave/bench/Makefile<br /> siva12 Wed, 16 Dec 2009 11:58:52 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=8 added testbech file https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=7 <div><strong>Rev 7 - siva12</strong> (1 file(s) modified)</div><div>added testbech file</div>+ /spislave/trunk/spislave/bench/tb_spigpio.v<br /> siva12 Wed, 16 Dec 2009 11:41:50 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=7 added header https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=6 <div><strong>Rev 6 - siva12</strong> (1 file(s) modified)</div><div>added header</div>+ /spislave/trunk/spislave/rtl/verilog/lgpl-3.0.txt<br /> siva12 Wed, 16 Dec 2009 11:16:42 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=6 added header https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=5 <div><strong>Rev 5 - siva12</strong> (1 file(s) modified)</div><div>added header</div>~ /spislave/trunk/spislave/rtl/verilog/spigpio.v<br /> siva12 Wed, 16 Dec 2009 11:05:36 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=5 added rtl code for spislave https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=4 <div><strong>Rev 4 - siva12</strong> (1 file(s) modified)</div><div>added rtl code for spislave</div>+ /spislave/trunk/spislave/rtl/verilog/spigpio.v<br /> siva12 Wed, 16 Dec 2009 05:24:00 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=4 added block diagram of spislave fpga board https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=3 <div><strong>Rev 3 - siva12</strong> (2 file(s) modified)</div><div>added block diagram of spislave fpga board</div>+ /spislave/trunk/spislave/doc/FPGA1.dia<br />+ /spislave/trunk/spislave/doc/FPGA1.jpeg<br /> siva12 Tue, 08 Dec 2009 05:09:39 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=3 created folders as per oopencores standard https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=2 <div><strong>Rev 2 - siva12</strong> (30 file(s) modified)</div><div>created folders as per oopencores standard</div>+ /spislave/trunk/spislave<br />+ /spislave/trunk/spislave/backend<br />+ /spislave/trunk/spislave/backend/zilogic<br />+ /spislave/trunk/spislave/bench<br />+ /spislave/trunk/spislave/doc<br />+ /spislave/trunk/spislave/doc/src<br />+ /spislave/trunk/spislave/rtl<br />+ /spislave/trunk/spislave/rtl/verilog<br />+ /spislave/trunk/spislave/rtl/vhdl<br />+ /spislave/trunk/spislave/sim<br />+ /spislave/trunk/spislave/sim/gate_sim<br />+ /spislave/trunk/spislave/sim/gate_sim/bin<br />+ /spislave/trunk/spislave/sim/gate_sim/log<br />+ /spislave/trunk/spislave/sim/gate_sim/out<br />+ /spislave/trunk/spislave/sim/gate_sim/run<br />+ /spislave/trunk/spislave/sim/gate_sim/src<br />+ /spislave/trunk/spislave/sim/rtl_sim<br />+ /spislave/trunk/spislave/sim/rtl_sim/bin<br />+ /spislave/trunk/spislave/sim/rtl_sim/log<br />+ /spislave/trunk/spislave/sim/rtl_sim/out<br />+ /spislave/trunk/spislave/sim/rtl_sim/run<br />+ /spislave/trunk/spislave/sim/rtl_sim/src<br />+ /spislave/trunk/spislave/sw<br />+ /spislave/trunk/spislave/syn<br />+ /spislave/trunk/spislave/syn/zilogic<br />+ /spislave/trunk/spislave/syn/zilogic/bin<br />+ /spislave/trunk/spislave/syn/zilogic/log<br />+ /spislave/trunk/spislave/syn/zilogic/out<br />+ /spislave/trunk/spislave/syn/zilogic/run<br />+ /spislave/trunk/spislave/syn/zilogic/src<br /> siva12 Tue, 08 Dec 2009 04:49:31 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=2 The project and the structure was created https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=1 <div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /spislave<br />+ /spislave/branches<br />+ /spislave/tags<br />+ /spislave/trunk<br /> root Mon, 07 Dec 2009 14:50:03 +0100 https://opencores.org/websvn//websvn/revision?repname=spislave&path=%2Fspislave%2F&rev=1

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