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uart2bus
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https://opencores.org/websvn//websvn/listing?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&
Wed, 11 Mar 2026 04:10:18 +0100
FeedCreator 1.7.2
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Adding simplified BSD license file
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=14
<div><strong>Rev 14 - motilito</strong> (1 file(s) modified)</div><div>Adding simplified BSD license file</div>+ /uart2bus/trunk/license.txt<br />
motilito
Thu, 19 Jan 2017 03:52:30 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=14
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VHDL version:
- Add GHDL support for automated testbenches.
- Migrate to ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=13
<div><strong>Rev 13 - smuller</strong> (14 file(s) modified)</div><div>VHDL version:<br />
- Add GHDL support for automated testbenches.<br />
- Migrate to ...</div>~ /uart2bus/trunk/vhdl/bench/helpers/helpers_pkg.vhd<br />~ /uart2bus/trunk/vhdl/bench/helpers/regFileModel.vhd<br />~ /uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd<br />~ /uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd<br />~ /uart2bus/trunk/vhdl/rtl/baudGen.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartParser.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartRx.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartTx.vhd<br />+ /uart2bus/trunk/vhdl/sim/ghdl<br />+ /uart2bus/trunk/vhdl/sim/ghdl/shell_tools.sh<br />+ /uart2bus/trunk/vhdl/sim/ghdl/uart2BusTop_bin_tb.sav<br />+ /uart2bus/trunk/vhdl/sim/ghdl/uart2BusTop_txt_tb.sav<br />+ /uart2bus/trunk/vhdl/sim/ghdl/uart2bus_bin_build.sh<br />+ /uart2bus/trunk/vhdl/sim/ghdl/uart2bus_txt_build.sh<br />
smuller
Sat, 20 Feb 2016 14:15:39 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=13
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Updated Verilog implementation to sync with VHDL to include internal ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=12
<div><strong>Rev 12 - motilito</strong> (7 file(s) modified)</div><div>Updated Verilog implementation to sync with VHDL to include internal ...</div>~ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />~ /uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/uart_tasks.v<br />~ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />~ /uart2bus/trunk/verilog/rtl/uart_parser.v<br />
motilito
Sat, 25 Feb 2012 10:48:40 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=12
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VHDL version:
- Add a request-grant mechanism. This will permit to ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=11
<div><strong>Rev 11 - smuller</strong> (28 file(s) modified)</div><div>VHDL version:<br />
- Add a request-grant mechanism. This will permit to ...</div>~ /uart2bus/trunk/vhdl<br />~ /uart2bus/trunk/vhdl/bench<br />+ /uart2bus/trunk/vhdl/bench/helpers<br />+ /uart2bus/trunk/vhdl/bench/helpers/helpers_pkg.vhd<br />+ /uart2bus/trunk/vhdl/bench/helpers/regFileModel.vhd<br />- /uart2bus/trunk/vhdl/bench/regFileModel.vhd<br />~ /uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd<br />~ /uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd<br />~ /uart2bus/trunk/vhdl/rtl/baudGen.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uart2BusTop.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uart2BusTop_pkg.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartParser.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartRx.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartTop.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartTx.vhd<br />~ /uart2bus/trunk/vhdl/sim/modelsim<br />+ /uart2bus/trunk/vhdl/sim/modelsim/uart2bus_bin_sim.bat<br />+ /uart2bus/trunk/vhdl/sim/modelsim/uart2bus_bin_sim.tcl<br />+ /uart2bus/trunk/vhdl/sim/modelsim/uart2bus_txt_sim.bat<br />+ /uart2bus/trunk/vhdl/sim/modelsim/uart2bus_txt_sim.tcl<br />+ /uart2bus/trunk/vhdl/sim/modelsim/wave_uart2bus_bin.do<br />+ /uart2bus/trunk/vhdl/sim/modelsim/wave_uart2bus_txt.do<br />+ /uart2bus/trunk/vhdl/sim/test.bin<br />+ /uart2bus/trunk/vhdl/sim/test.txt<br />~ /uart2bus/trunk/vhdl/syn/xilinx<br />~ /uart2bus/trunk/vhdl/syn/xilinx/uart2bus.xise<br />- /uart2bus/trunk/vhdl/test.bin<br />- /uart2bus/trunk/vhdl/test.txt<br />
smuller
Thu, 23 Feb 2012 19:20:39 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=11
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VHDL version: corrected problems in the UART modules that prevented ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=10
<div><strong>Rev 10 - smuller</strong> (2 file(s) modified)</div><div>VHDL version: corrected problems in the UART modules that prevented ...</div>~ /uart2bus/trunk/vhdl/rtl/uartRx.vhd<br />~ /uart2bus/trunk/vhdl/rtl/uartTx.vhd<br />
smuller
Wed, 23 Nov 2011 21:11:00 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=10
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Corrected problems in the UART modules that prevented it to ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=9
<div><strong>Rev 9 - motilito</strong> (2 file(s) modified)</div><div>Corrected problems in the UART modules that prevented it to ...</div>~ /uart2bus/trunk/verilog/rtl/uart_rx.v<br />~ /uart2bus/trunk/verilog/rtl/uart_tx.v<br />
motilito
Tue, 22 Nov 2011 10:20:52 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=9
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Updated core description document to include Lattice device synthesis results.
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=8
<div><strong>Rev 8 - motilito</strong> (1 file(s) modified)</div><div>Updated core description document to include Lattice device synthesis results.</div>~ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />
motilito
Fri, 15 Apr 2011 05:42:07 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=8
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Updated the Scilab script for Scilab 5.3 version. Previous versions ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=7
<div><strong>Rev 7 - motilito</strong> (1 file(s) modified)</div><div>Updated the Scilab script for Scilab 5.3 version. Previous versions ...</div>~ /uart2bus/trunk/scilab/calc_baud_gen.sce<br />
motilito
Thu, 24 Mar 2011 20:50:31 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=7
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Commit VHDL description source with basic test benches
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=6
<div><strong>Rev 6 - smuller</strong> (14 file(s) modified)</div><div>Commit VHDL description source with basic test benches</div>+ /uart2bus/trunk/vhdl/bench/regFileModel.vhd<br />+ /uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd<br />+ /uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd<br />+ /uart2bus/trunk/vhdl/rtl/baudGen.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uart2BusTop.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uartParser.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uartRx.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uartTop.vhd<br />+ /uart2bus/trunk/vhdl/rtl/uartTx.vhd<br />+ /uart2bus/trunk/vhdl/sim/modelsim<br />+ /uart2bus/trunk/vhdl/syn/xilinx<br />+ /uart2bus/trunk/vhdl/syn/xilinx/uart2bus.xise<br />+ /uart2bus/trunk/vhdl/test.bin<br />+ /uart2bus/trunk/vhdl/test.txt<br />
smuller
Sun, 18 Jul 2010 11:22:37 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=6
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Add structure for VHDL (verilog similar tree).
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=5
<div><strong>Rev 5 - smuller</strong> (5 file(s) modified)</div><div>Add structure for VHDL (verilog similar tree).</div>+ /uart2bus/trunk/vhdl<br />+ /uart2bus/trunk/vhdl/bench<br />+ /uart2bus/trunk/vhdl/rtl<br />+ /uart2bus/trunk/vhdl/sim<br />+ /uart2bus/trunk/vhdl/syn<br />
smuller
Tue, 06 Jul 2010 18:00:14 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=5
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Corrected some problems in the binary mode protocol test bench. ...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=4
<div><strong>Rev 4 - motilito</strong> (13 file(s) modified)</div><div>Corrected some problems in the binary mode protocol test bench. ...</div>~ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />- /uart2bus/trunk/verilog/bench/readme.txt<br />+ /uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v<br />- /uart2bus/trunk/verilog/bench/Test Bench Binary Mode - tb_uart2bus_top.v<br />- /uart2bus/trunk/verilog/bench/Test Bench Text Mode - tb_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />- /uart2bus/trunk/verilog/sim/icarus/block.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/block_bin.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/block_txt.cfg<br />- /uart2bus/trunk/verilog/sim/icarus/compile.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/compile_bin.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/compile_txt.bat<br />
motilito
Fri, 02 Apr 2010 19:54:36 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=4
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...
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=3
<div><strong>Rev 3 - motilito</strong> (1 file(s) modified)</div><div>...</div>~ /uart2bus/trunk/verilog/rtl/baud_gen.v<br />
motilito
Mon, 15 Feb 2010 13:49:55 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=3
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Uploaded the initial project version.
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=2
<div><strong>Rev 2 - motilito</strong> (35 file(s) modified)</div><div>Uploaded the initial project version.</div>+ /uart2bus/trunk/doc<br />+ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />+ /uart2bus/trunk/scilab<br />+ /uart2bus/trunk/scilab/calc_baud_gen.sce<br />+ /uart2bus/trunk/verilog<br />+ /uart2bus/trunk/verilog/bench<br />+ /uart2bus/trunk/verilog/bench/readme.txt<br />+ /uart2bus/trunk/verilog/bench/reg_file_model.v<br />+ /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/Test Bench Binary Mode - tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/Test Bench Text Mode - tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/timescale.v<br />+ /uart2bus/trunk/verilog/bench/uart_tasks.v<br />+ /uart2bus/trunk/verilog/rtl<br />+ /uart2bus/trunk/verilog/rtl/baud_gen.v<br />+ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />+ /uart2bus/trunk/verilog/rtl/uart_parser.v<br />+ /uart2bus/trunk/verilog/rtl/uart_rx.v<br />+ /uart2bus/trunk/verilog/rtl/uart_top.v<br />+ /uart2bus/trunk/verilog/rtl/uart_tx.v<br />+ /uart2bus/trunk/verilog/sim<br />+ /uart2bus/trunk/verilog/sim/icarus<br />+ /uart2bus/trunk/verilog/sim/icarus/block.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/compile.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/gtk.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/run.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/test.bin<br />+ /uart2bus/trunk/verilog/sim/icarus/test.txt<br />+ /uart2bus/trunk/verilog/syn<br />+ /uart2bus/trunk/verilog/syn/altera<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus.qpf<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus.qws<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus_top.qsf<br />+ /uart2bus/trunk/verilog/syn/xilinx<br />+ /uart2bus/trunk/verilog/syn/xilinx/uart2bus.xise<br />
motilito
Mon, 15 Feb 2010 12:36:00 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=2
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The project and the structure was created
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=1
<div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /uart2bus<br />+ /uart2bus/branches<br />+ /uart2bus/tags<br />+ /uart2bus/trunk<br />
root
Fri, 12 Feb 2010 19:00:03 +0100
https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2F&rev=1
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