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uart2bus WebSVN RSS feed - uart2bus https://opencores.org/websvn//websvn/listing?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F& Wed, 07 Jun 2023 05:52:08 +0100 FeedCreator 1.7.2 Updated Verilog implementation to sync with VHDL to include internal ... https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=12 <div><strong>Rev 12 - motilito</strong> (7 file(s) modified)</div><div>Updated Verilog implementation to sync with VHDL to include internal ...</div>~ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />~ /uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/bench/uart_tasks.v<br />~ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />~ /uart2bus/trunk/verilog/rtl/uart_parser.v<br /> motilito Sat, 25 Feb 2012 10:48:40 +0100 https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=12 Corrected problems in the UART modules that prevented it to ... https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=9 <div><strong>Rev 9 - motilito</strong> (2 file(s) modified)</div><div>Corrected problems in the UART modules that prevented it to ...</div>~ /uart2bus/trunk/verilog/rtl/uart_rx.v<br />~ /uart2bus/trunk/verilog/rtl/uart_tx.v<br /> motilito Tue, 22 Nov 2011 10:20:52 +0100 https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=9 Corrected some problems in the binary mode protocol test bench. ... https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=4 <div><strong>Rev 4 - motilito</strong> (13 file(s) modified)</div><div>Corrected some problems in the binary mode protocol test bench. ...</div>~ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />- /uart2bus/trunk/verilog/bench/readme.txt<br />+ /uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v<br />- /uart2bus/trunk/verilog/bench/Test Bench Binary Mode - tb_uart2bus_top.v<br />- /uart2bus/trunk/verilog/bench/Test Bench Text Mode - tb_uart2bus_top.v<br />~ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />- /uart2bus/trunk/verilog/sim/icarus/block.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/block_bin.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/block_txt.cfg<br />- /uart2bus/trunk/verilog/sim/icarus/compile.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/compile_bin.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/compile_txt.bat<br /> motilito Fri, 02 Apr 2010 19:54:36 +0100 https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=4 ... https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=3 <div><strong>Rev 3 - motilito</strong> (1 file(s) modified)</div><div>...</div>~ /uart2bus/trunk/verilog/rtl/baud_gen.v<br /> motilito Mon, 15 Feb 2010 13:49:55 +0100 https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=3 Uploaded the initial project version. https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=2 <div><strong>Rev 2 - motilito</strong> (35 file(s) modified)</div><div>Uploaded the initial project version.</div>+ /uart2bus/trunk/doc<br />+ /uart2bus/trunk/doc/UART to Bus Core Specifications.pdf<br />+ /uart2bus/trunk/scilab<br />+ /uart2bus/trunk/scilab/calc_baud_gen.sce<br />+ /uart2bus/trunk/verilog<br />+ /uart2bus/trunk/verilog/bench<br />+ /uart2bus/trunk/verilog/bench/readme.txt<br />+ /uart2bus/trunk/verilog/bench/reg_file_model.v<br />+ /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/Test Bench Binary Mode - tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/Test Bench Text Mode - tb_uart2bus_top.v<br />+ /uart2bus/trunk/verilog/bench/timescale.v<br />+ /uart2bus/trunk/verilog/bench/uart_tasks.v<br />+ /uart2bus/trunk/verilog/rtl<br />+ /uart2bus/trunk/verilog/rtl/baud_gen.v<br />+ /uart2bus/trunk/verilog/rtl/uart2bus_top.v<br />+ /uart2bus/trunk/verilog/rtl/uart_parser.v<br />+ /uart2bus/trunk/verilog/rtl/uart_rx.v<br />+ /uart2bus/trunk/verilog/rtl/uart_top.v<br />+ /uart2bus/trunk/verilog/rtl/uart_tx.v<br />+ /uart2bus/trunk/verilog/sim<br />+ /uart2bus/trunk/verilog/sim/icarus<br />+ /uart2bus/trunk/verilog/sim/icarus/block.cfg<br />+ /uart2bus/trunk/verilog/sim/icarus/compile.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/gtk.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/run.bat<br />+ /uart2bus/trunk/verilog/sim/icarus/test.bin<br />+ /uart2bus/trunk/verilog/sim/icarus/test.txt<br />+ /uart2bus/trunk/verilog/syn<br />+ /uart2bus/trunk/verilog/syn/altera<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus.qpf<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus.qws<br />+ /uart2bus/trunk/verilog/syn/altera/uart2bus_top.qsf<br />+ /uart2bus/trunk/verilog/syn/xilinx<br />+ /uart2bus/trunk/verilog/syn/xilinx/uart2bus.xise<br /> motilito Mon, 15 Feb 2010 12:36:00 +0100 https://opencores.org/websvn//websvn/revision?repname=uart2bus&path=%2Fuart2bus%2Ftrunk%2Fverilog%2F&rev=2
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