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versatile_fifo WebSVN RSS feed - versatile_fifo https://opencores.org/websvn//websvn/listing?repname=versatile_fifo&path=%2Fversatile_fifo%2F& Thu, 28 Mar 2024 21:46:56 +0100 FeedCreator 1.7.2 fixed SYN directives https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=32 <div><strong>Rev 32 - marcus.erlandsson</strong> (3 file(s) modified)</div><div>fixed SYN directives</div>~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v<br /> marcus.erlandsson Thu, 04 Nov 2010 10:02:53 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=32 port map https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=31 <div><strong>Rev 31 - unneback</strong> (2 file(s) modified)</div><div>port map</div>~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v<br />~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_top.v<br /> unneback Wed, 25 Aug 2010 17:11:15 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=31 port map https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=30 <div><strong>Rev 30 - unneback</strong> (2 file(s) modified)</div><div>port map</div>~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v<br />~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_top.v<br /> unneback Wed, 25 Aug 2010 16:38:57 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=30 ACTEL syn define https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=29 <div><strong>Rev 29 - unneback</strong> (2 file(s) modified)</div><div>ACTEL syn define</div>~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v<br />~ /versatile_fifo/trunk/rtl/verilog/Makefile<br /> unneback Tue, 17 Aug 2010 19:15:33 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=29 ACTEL async dual way FIFO https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=28 <div><strong>Rev 28 - unneback</strong> (4 file(s) modified)</div><div>ACTEL async dual way FIFO</div>+ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v<br />~ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_top.v<br />~ /versatile_fifo/trunk/rtl/verilog/Makefile<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v<br /> unneback Tue, 10 Aug 2010 09:47:10 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=28 initial commit, dual way simplex FIFO https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=27 <div><strong>Rev 27 - unneback</strong> (1 file(s) modified)</div><div>initial commit, dual way simplex FIFO</div>+ /versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_top.v<br /> unneback Mon, 09 Aug 2010 18:16:56 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=27 added ACTEL synthesis directive as define, +ACTEL https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=26 <div><strong>Rev 26 - unneback</strong> (6 file(s) modified)</div><div>added ACTEL synthesis directive as define, +ACTEL</div>~ /versatile_fifo/trunk/rtl/verilog/Makefile<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v<br /> unneback Mon, 09 Aug 2010 18:15:29 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=26 DFF SR as separate logic https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=25 <div><strong>Rev 25 - unneback</strong> (2 file(s) modified)</div><div>DFF SR as separate logic</div>+ /versatile_fifo/trunk/rtl/verilog/dff_sr.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v<br /> unneback Mon, 22 Mar 2010 22:43:04 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=25 updated fifo interfaces with re/rd and we/wr https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=24 <div><strong>Rev 24 - unneback</strong> (2 file(s) modified)</div><div>updated fifo interfaces with re/rd and we/wr</div>~ /versatile_fifo/trunk/rtl/verilog/async_fifo_mq.v<br />~ /versatile_fifo/trunk/rtl/verilog/async_fifo_mq_md.v<br /> unneback Mon, 22 Mar 2010 08:04:27 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=24 ... https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=23 <div><strong>Rev 23 - unneback</strong> (2 file(s) modified)</div><div>...</div>~ /versatile_fifo/trunk/rtl/verilog/async_fifo_mq.v<br />+ /versatile_fifo/trunk/rtl/verilog/async_fifo_mq_md.v<br /> unneback Fri, 19 Mar 2010 19:48:01 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=23 async fifo with multiple queues https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=22 <div><strong>Rev 22 - unneback</strong> (2 file(s) modified)</div><div>async fifo with multiple queues</div>+ /versatile_fifo/trunk/rtl/verilog/async_fifo_mq.v<br />~ /versatile_fifo/trunk/rtl/verilog/Makefile<br /> unneback Fri, 19 Mar 2010 19:06:03 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=22 added DFF SR https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=21 <div><strong>Rev 21 - unneback</strong> (3 file(s) modified)</div><div>added DFF SR</div>+ /versatile_fifo/trunk/rtl/verilog/adr_gen.xls<br />~ /versatile_fifo/trunk/rtl/verilog/Makefile<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v<br /> unneback Fri, 05 Mar 2010 21:38:01 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=21 ... https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=20 <div><strong>Rev 20 - unneback</strong> (2 file(s) modified)</div><div>...</div>+ /versatile_fifo/trunk/syn<br />+ /versatile_fifo/trunk/syn/altera<br /> unneback Fri, 05 Mar 2010 14:32:21 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=20 DFF with async clear and set for Altera cycloneIV https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=19 <div><strong>Rev 19 - unneback</strong> (4 file(s) modified)</div><div>DFF with async clear and set for Altera cycloneIV</div>+ /versatile_fifo/trunk/backend<br />+ /versatile_fifo/trunk/backend/altera<br />+ /versatile_fifo/trunk/backend/altera/cycloneIV<br />+ /versatile_fifo/trunk/backend/altera/cycloneIV/dff_sr.v<br /> unneback Thu, 04 Mar 2010 08:26:47 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=19 ADDR and DATA width set to 8 resp 32 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=18 <div><strong>Rev 18 - unneback</strong> (5 file(s) modified)</div><div>ADDR and DATA width set to 8 resp 32</div>~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v<br /> unneback Wed, 03 Mar 2010 18:32:54 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=18 based on updated versatile counter https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=17 <div><strong>Rev 17 - unneback</strong> (10 file(s) modified)</div><div>based on updated versatile counter</div>~ /versatile_fifo/trunk/doc/src/versatile_fifo.odt<br />~ /versatile_fifo/trunk/doc/versatile_fifo.pdf<br />+ /versatile_fifo/trunk/rtl/verilog/gray_counter.xls<br />~ /versatile_fifo/trunk/rtl/verilog/Makefile<br />+ /versatile_fifo/trunk/rtl/verilog/sd_counter.xls<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v<br />+ /versatile_fifo/trunk/rtl/verilog/vfifo.kpf<br /> unneback Sat, 27 Feb 2010 20:05:41 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=17 changed power of two style https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=16 <div><strong>Rev 16 - unneback</strong> (1 file(s) modified)</div><div>changed power of two style</div>~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v<br /> unneback Tue, 09 Jun 2009 10:13:37 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=16 doc updated gray_counter_defines added dual port RAM updated https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=15 <div><strong>Rev 15 - unneback</strong> (6 file(s) modified)</div><div>doc updated<br /> gray_counter_defines added<br /> dual port RAM updated</div>~ /versatile_fifo/trunk/doc/src/versatile_fifo.odt<br />~ /versatile_fifo/trunk/doc/versatile_fifo.pdf<br />+ /versatile_fifo/trunk/rtl/verilog/gray_counter_defines.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v<br />~ /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v<br /> unneback Fri, 05 Jun 2009 16:37:05 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=15 added PDF https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=14 <div><strong>Rev 14 - unneback</strong> (2 file(s) modified)</div><div>added PDF</div>~ /versatile_fifo/trunk/doc/src/versatile_fifo.odt<br />+ /versatile_fifo/trunk/doc/versatile_fifo.pdf<br /> unneback Wed, 22 Apr 2009 09:59:27 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=14 adr update https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=13 <div><strong>Rev 13 - unneback</strong> (1 file(s) modified)</div><div>adr update</div>~ /versatile_fifo/trunk/rtl/verilog/sd_fifo.v<br /> unneback Tue, 21 Apr 2009 07:53:06 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_fifo&path=%2Fversatile_fifo%2F&rev=13
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