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versatile_library WebSVN RSS feed - versatile_library https://opencores.org/websvn//websvn/listing?repname=versatile_library&path=%2Fversatile_library%2F& Mon, 04 Jul 2022 10:02:58 +0100 FeedCreator 1.7.2 corrected EXT unit, rewrite of FF1, FL1 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=57 <div><strong>Rev 57 - unneback</strong> (2 file(s) modified)</div><div>corrected EXT unit, rewrite of FF1, FL1</div>~ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br /> unneback Tue, 14 Jun 2011 07:21:21 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=57 WB B4 RAM we fix https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=56 <div><strong>Rev 56 - unneback</strong> (4 file(s) modified)</div><div>WB B4 RAM we fix</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Wed, 01 Jun 2011 14:44:06 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=56 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=55 <div><strong>Rev 55 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:57:49 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=55 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=54 <div><strong>Rev 54 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:57:15 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=54 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=53 <div><strong>Rev 53 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:56:44 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=53 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=52 <div><strong>Rev 52 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:56:04 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=52 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=51 <div><strong>Rev 51 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:44:14 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=51 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=50 <div><strong>Rev 50 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:30:27 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=50 added WB_B4RAM with byte enable https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=49 <div><strong>Rev 49 - unneback</strong> (5 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 30 May 2011 07:21:10 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=49 wb updated https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=48 <div><strong>Rev 48 - unneback</strong> (9 file(s) modified)</div><div>wb updated</div>~ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Mon, 23 May 2011 13:29:15 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=48 added help program for LFSR counters https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=47 <div><strong>Rev 47 - unneback</strong> (3 file(s) modified)</div><div>added help program for LFSR counters</div>+ /versatile_library/trunk/misc<br />+ /versatile_library/trunk/misc/VersatileCounter.class.php<br />+ /versatile_library/trunk/misc/VersatileCounter.php<br /> unneback Thu, 17 Feb 2011 10:22:51 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=47 updated parity https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=46 <div><strong>Rev 46 - unneback</strong> (4 file(s) modified)</div><div>updated parity</div>~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Wed, 16 Feb 2011 08:52:56 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=46 updated timing in io models https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=45 <div><strong>Rev 45 - unneback</strong> (4 file(s) modified)</div><div>updated timing in io models</div>~ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Mon, 14 Feb 2011 14:43:36 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=45 added target independet IO functionns https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=44 <div><strong>Rev 44 - unneback</strong> (8 file(s) modified)</div><div>added target independet IO functionns</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />+ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Fri, 11 Feb 2011 14:53:20 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=44 added logic for parity generation and check https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=43 <div><strong>Rev 43 - unneback</strong> (5 file(s) modified)</div><div>added logic for parity generation and check</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Mon, 07 Feb 2011 11:42:43 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=43 updated mux_andor https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=42 <div><strong>Rev 42 - unneback</strong> (6 file(s) modified)</div><div>updated mux_andor</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Thu, 03 Feb 2011 11:51:01 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=42 typo in registers.v https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=41 <div><strong>Rev 41 - unneback</strong> (2 file(s) modified)</div><div>typo in registers.v</div>~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br /> unneback Thu, 03 Feb 2011 10:18:17 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=41 new build environment with custom.v added as a result file https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=40 <div><strong>Rev 40 - unneback</strong> (34 file(s) modified)</div><div>new build environment with custom.v added as a result file</div>~ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_l1_l2.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_set_rew.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_q_zq_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_zq_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_clear.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_gray.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_gray_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_gray_ce_bin.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_clear_q.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_q.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_q_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_rew_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/counters.v<br />+ /versatile_library/trunk/rtl/verilog/CSV.class.php<br />+ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br />+ /versatile_library/trunk/rtl/verilog/versatile_counter_generator.php<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Thu, 03 Feb 2011 10:01:19 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=40 added simple port prio based wb arbiter https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=39 <div><strong>Rev 39 - unneback</strong> (4 file(s) modified)</div><div>added simple port prio based wb arbiter</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Wed, 02 Feb 2011 13:02:58 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=39 updated andor mux https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=38 <div><strong>Rev 38 - unneback</strong> (4 file(s) modified)</div><div>updated andor mux</div>~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Wed, 02 Feb 2011 12:59:29 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2F&rev=38
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