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versatile_library
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https://opencores.org/websvn//websvn/listing?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&
Wed, 11 Mar 2026 18:25:17 +0100
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no arbiter in wb_b3_ram_be
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=70
<div><strong>Rev 70 - unneback</strong> (4 file(s) modified)</div><div>no arbiter in wb_b3_ram_be</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Thu, 11 Aug 2011 09:50:52 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=70
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no arbiter in wb_b3_ram_be
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=69
<div><strong>Rev 69 - unneback</strong> (4 file(s) modified)</div><div>no arbiter in wb_b3_ram_be</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Thu, 11 Aug 2011 09:49:00 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=69
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ram_be updated to optional mem_size
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=68
<div><strong>Rev 68 - unneback</strong> (5 file(s) modified)</div><div>ram_be updated to optional mem_size</div>~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Thu, 11 Aug 2011 09:40:14 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=68
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support up to 8 wbm on arbiter
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=67
<div><strong>Rev 67 - unneback</strong> (4 file(s) modified)</div><div>support up to 8 wbm on arbiter</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Wed, 10 Aug 2011 10:07:08 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=67
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RAM_BE ack_o vector
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=66
<div><strong>Rev 66 - unneback</strong> (4 file(s) modified)</div><div>RAM_BE ack_o vector</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Sun, 03 Jul 2011 11:14:47 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=66
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RAM_BE system verilog version
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=65
<div><strong>Rev 65 - unneback</strong> (4 file(s) modified)</div><div>RAM_BE system verilog version</div>~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />
unneback
Sun, 03 Jul 2011 10:20:42 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=65
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SPR reset value
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=64
<div><strong>Rev 64 - unneback</strong> (4 file(s) modified)</div><div>SPR reset value</div>~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />
unneback
Sun, 03 Jul 2011 10:02:37 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=64
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WB_B3_RAM_BE updates, bte port map + define dependency
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=63
<div><strong>Rev 63 - unneback</strong> (4 file(s) modified)</div><div>WB_B3_RAM_BE updates, bte port map + define dependency</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Sun, 03 Jul 2011 09:55:02 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=63
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WB_B3_RAM_BE updates, bte port map + define dependency
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=62
<div><strong>Rev 62 - unneback</strong> (2 file(s) modified)</div><div>WB_B3_RAM_BE updates, bte port map + define dependency</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />
unneback
Sun, 03 Jul 2011 09:45:55 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=62
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WB_B3_RAM_BE updates, bte port map + define dependency
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=61
<div><strong>Rev 61 - unneback</strong> (5 file(s) modified)</div><div>WB_B3_RAM_BE updates, bte port map + define dependency</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Sun, 03 Jul 2011 09:35:29 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=61
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added wb b3 byte enable memory, added test in makefile ...
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=60
<div><strong>Rev 60 - unneback</strong> (8 file(s) modified)</div><div>added wb b3 byte enable memory, added test in makefile ...</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Fri, 01 Jul 2011 14:13:56 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=60
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added WB RAM B3 with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=59
<div><strong>Rev 59 - unneback</strong> (5 file(s) modified)</div><div>added WB RAM B3 with byte enable</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Thu, 30 Jun 2011 14:00:47 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=59
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corrected EXT unit, rewrite of FF1, FL1
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=58
<div><strong>Rev 58 - unneback</strong> (2 file(s) modified)</div><div>corrected EXT unit, rewrite of FF1, FL1</div>~ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />
unneback
Tue, 14 Jun 2011 07:22:28 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=58
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corrected EXT unit, rewrite of FF1, FL1
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=57
<div><strong>Rev 57 - unneback</strong> (2 file(s) modified)</div><div>corrected EXT unit, rewrite of FF1, FL1</div>~ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />
unneback
Tue, 14 Jun 2011 07:21:21 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=57
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WB B4 RAM we fix
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=56
<div><strong>Rev 56 - unneback</strong> (4 file(s) modified)</div><div>WB B4 RAM we fix</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Wed, 01 Jun 2011 14:44:06 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=56
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added WB_B4RAM with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=55
<div><strong>Rev 55 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Mon, 30 May 2011 07:57:49 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=55
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added WB_B4RAM with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=54
<div><strong>Rev 54 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Mon, 30 May 2011 07:57:15 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=54
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added WB_B4RAM with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=53
<div><strong>Rev 53 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Mon, 30 May 2011 07:56:44 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=53
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added WB_B4RAM with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=52
<div><strong>Rev 52 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Mon, 30 May 2011 07:56:04 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=52
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added WB_B4RAM with byte enable
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=51
<div><strong>Rev 51 - unneback</strong> (4 file(s) modified)</div><div>added WB_B4RAM with byte enable</div>~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Mon, 30 May 2011 07:44:14 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2F&rev=51
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