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versatile_library WebSVN RSS feed - versatile_library https://opencores.org/websvn//websvn/listing?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2FMakefile& Thu, 28 Mar 2024 19:13:08 +0100 FeedCreator 1.7.2 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=26 <div><strong>Rev 26 - unneback</strong> (4 file(s) modified)</div><div>typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q</div>+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_clear_q.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_q.csv<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br /> unneback Wed, 15 Dec 2010 10:32:45 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=26 added sync FIFO https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=25 <div><strong>Rev 25 - unneback</strong> (7 file(s) modified)</div><div>added sync FIFO</div>+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_q_zq_l1.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_zq_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Tue, 14 Dec 2010 20:58:04 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=25 added binary counters https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 <div><strong>Rev 22 - unneback</strong> (6 file(s) modified)</div><div>added binary counters</div>+ /versatile_library/trunk/rtl/verilog/cnt_bin.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_clear.csv<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br /> unneback Sun, 12 Dec 2010 17:25:59 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 naming convention vl_ https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=18 <div><strong>Rev 18 - unneback</strong> (24 file(s) modified)</div><div>naming convention vl_</div>~ /versatile_library/trunk/doc/src/Versatile_library.odt<br />~ /versatile_library/trunk/doc/Versatile_library.pdf<br />+ /versatile_library/trunk/rtl/verilog/arith.v<br />~ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_set_rew.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_l1.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_gray.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_gray_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_gray_ce_bin.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_rew_l1.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/cnt_lfsr_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/counters.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Fri, 10 Dec 2010 10:09:44 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=18 added wishbone comliant modules https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=12 <div><strong>Rev 12 - unneback</strong> (5 file(s) modified)</div><div>added wishbone comliant modules</div>~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />+ /versatile_library/trunk/rtl/verilog/wb.v<br /> unneback Thu, 30 Sep 2010 10:25:35 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=12 memories added https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=5 <div><strong>Rev 5 - unneback</strong> (6 file(s) modified)</div><div>memories added</div>~ /versatile_library/trunk/doc/src/Versatile_library.odt<br />~ /versatile_library/trunk/doc/Versatile_library.pdf<br />~ /versatile_library/trunk/rtl/verilog/counters.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />+ /versatile_library/trunk/rtl/verilog/memories.v<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br /> unneback Tue, 14 Sep 2010 18:49:32 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=5 added counters https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=4 <div><strong>Rev 4 - unneback</strong> (15 file(s) modified)</div><div>added counters</div>~ /versatile_library/trunk/doc/src/Versatile_library.odt<br />~ /versatile_library/trunk/doc/Versatile_library.pdf<br />~ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_set_rew.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_l1.csv<br />- /versatile_library/trunk/rtl/verilog/cnt_gray.csv<br />- /versatile_library/trunk/rtl/verilog/cnt_gray_bin_ce.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_gray_ce_bin.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_rew_l1.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_zq.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_zq.csv<br />~ /versatile_library/trunk/rtl/verilog/counters.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br /> unneback Fri, 10 Sep 2010 15:10:15 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=4 various updates counter added https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=3 <div><strong>Rev 3 - unneback</strong> (11 file(s) modified)</div><div>various updates<br /> counter added</div>~ /versatile_library/trunk/doc/src/Versatile_library.odt<br />+ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />+ /versatile_library/trunk/rtl/verilog/cnt_gray.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_gray_bin_ce.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_gray_ce.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr.csv<br />+ /versatile_library/trunk/rtl/verilog/cnt_lfsr_ce.csv<br />+ /versatile_library/trunk/rtl/verilog/counters.v<br />+ /versatile_library/trunk/rtl/verilog/Makefile<br />+ /versatile_library/trunk/rtl/verilog/registers.v<br />+ /versatile_library/trunk/rtl/verilog/versatile_counter_defines.v<br /> unneback Tue, 07 Sep 2010 19:54:40 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=3
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