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versatile_library
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https://opencores.org/websvn//websvn/listing?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2Fio.v&
Fri, 29 Mar 2024 05:45:16 +0100
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https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=139
<div><strong>Rev 139 - unneback</strong> (9 file(s) modified)</div><div>...</div>~ /versatile_library/trunk/rtl/verilog/clk_and_reset.v<br />+ /versatile_library/trunk/rtl/verilog/custom_defines.v<br />~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/registers.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />
unneback
Mon, 21 Nov 2011 17:46:18 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=139
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updated cache, write to cache from SDRAM needs fixing
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=136
<div><strong>Rev 136 - unneback</strong> (7 file(s) modified)</div><div>updated cache, write to cache from SDRAM needs fixing</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />~ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />~ /versatile_library/trunk/sim/rtl_sim/run/Makefile<br />
unneback
Sun, 02 Oct 2011 19:09:34 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=136
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updated timing in io models
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=45
<div><strong>Rev 45 - unneback</strong> (4 file(s) modified)</div><div>updated timing in io models</div>~ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />
unneback
Mon, 14 Feb 2011 14:43:36 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=45
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added target independet IO functionns
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=44
<div><strong>Rev 44 - unneback</strong> (8 file(s) modified)</div><div>added target independet IO functionns</div>~ /versatile_library/trunk/rtl/verilog/defines.v<br />+ /versatile_library/trunk/rtl/verilog/io.v<br />~ /versatile_library/trunk/rtl/verilog/logic.v<br />~ /versatile_library/trunk/rtl/verilog/Makefile<br />~ /versatile_library/trunk/rtl/verilog/versatile_library.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_actel.v<br />~ /versatile_library/trunk/rtl/verilog/versatile_library_altera.v<br />~ /versatile_library/trunk/rtl/verilog/wb.v<br />
unneback
Fri, 11 Feb 2011 14:53:20 +0100
https://opencores.org/websvn//websvn/revision?repname=versatile_library&path=%2Fversatile_library%2Ftrunk%2Frtl%2Fverilog%2F&rev=44
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