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wbuart32 WebSVN RSS feed - wbuart32 https://opencores.org/websvn//websvn/listing?repname=wbuart32&path=%2Fwbuart32%2F& Fri, 29 Mar 2024 14:50:41 +0100 FeedCreator 1.7.2 Formally verified the TXUART core (plus others) https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=26 <div><strong>Rev 26 - dgisselq</strong> (26 file(s) modified)</div><div>Formally verified the TXUART core (plus others)</div>~ /wbuart32/trunk/bench/cpp/helloworld.cpp<br />~ /wbuart32/trunk/bench/cpp/linetest.cpp<br />~ /wbuart32/trunk/bench/cpp/Makefile<br />~ /wbuart32/trunk/bench/cpp/mkspeech.cpp<br />~ /wbuart32/trunk/bench/cpp/speechtest.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.h<br />~ /wbuart32/trunk/bench/formal<br />~ /wbuart32/trunk/bench/formal/Makefile<br />~ /wbuart32/trunk/bench/formal/rxuartlite.sby<br />+ /wbuart32/trunk/bench/formal/txuart.sby<br />~ /wbuart32/trunk/bench/formal/txuartlite.sby<br />~ /wbuart32/trunk/bench/formal/ufifo.sby<br />~ /wbuart32/trunk/bench/verilog<br />~ /wbuart32/trunk/bench/verilog/Makefile<br />~ /wbuart32/trunk/doc/gpl-3.0.pdf<br />~ /wbuart32/trunk/doc/spec.pdf<br />~ /wbuart32/trunk/Makefile<br />~ /wbuart32/trunk/rtl<br />~ /wbuart32/trunk/rtl/Makefile<br />~ /wbuart32/trunk/rtl/rxuart.v<br />~ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />~ /wbuart32/trunk/rtl/txuartlite.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br /> dgisselq Tue, 19 Mar 2019 03:02:38 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=26 ... https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=25 <div><strong>Rev 25 - dgisselq</strong> (2 file(s) modified)</div><div>...</div>~ /wbuart32/trunk/bench/formal<br />+ /wbuart32/trunk/bench/formal/ufifo.sby<br /> dgisselq Wed, 29 Aug 2018 18:01:46 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=25 Fixed the broken TX interrupt flagg https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=24 <div><strong>Rev 24 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the broken TX interrupt flagg</div>~ /wbuart32/trunk/rtl/ufifo.v<br /> dgisselq Wed, 29 Aug 2018 17:53:57 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=24 Brought SVN repo up to date with github repo https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=23 <div><strong>Rev 23 - dgisselq</strong> (7 file(s) modified)</div><div>Brought SVN repo up to date with github repo</div>~ /wbuart32/trunk/bench/cpp/uartsim.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.h<br />~ /wbuart32/trunk/bench/formal/rxuartlite.sby<br />~ /wbuart32/trunk/bench/formal/txuartlite.sby<br />~ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br /> dgisselq Wed, 29 Aug 2018 17:39:43 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=23 Added formal methods via SymbiYosys https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=22 <div><strong>Rev 22 - dgisselq</strong> (6 file(s) modified)</div><div>Added formal methods via SymbiYosys</div>~ /wbuart32/trunk/bench/formal/Makefile<br />+ /wbuart32/trunk/bench/formal/rxuartlite.sby<br />+ /wbuart32/trunk/bench/formal/rxuartlite.ys<br />+ /wbuart32/trunk/bench/formal/txuartlite.sby<br />~ /wbuart32/trunk/bench/formal/txuartlite.ys<br />~ /wbuart32/trunk/bench/formal/ufifo.ys<br /> dgisselq Tue, 29 May 2018 19:13:27 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=22 Updates based upon Formal methods https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=21 <div><strong>Rev 21 - dgisselq</strong> (4 file(s) modified)</div><div>Updates based upon Formal methods</div>~ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuartlite.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br /> dgisselq Tue, 29 May 2018 19:11:53 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=21 Added yosys-smtbmc config files for formal proofs https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=20 <div><strong>Rev 20 - dgisselq</strong> (3 file(s) modified)</div><div>Added yosys-smtbmc config files for formal proofs</div>+ /wbuart32/trunk/bench/formal/Makefile<br />+ /wbuart32/trunk/bench/formal/txuartlite.ys<br />+ /wbuart32/trunk/bench/formal/ufifo.ys<br /> dgisselq Wed, 15 Nov 2017 23:51:15 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=20 Added a directory for formal info https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=19 <div><strong>Rev 19 - dgisselq</strong> (1 file(s) modified)</div><div>Added a directory for formal info</div>+ /wbuart32/trunk/bench/formal<br /> dgisselq Wed, 15 Nov 2017 23:50:27 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=19 Lots of updates. See the git log for details https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=18 <div><strong>Rev 18 - dgisselq</strong> (19 file(s) modified)</div><div>Lots of updates. See the git log for details</div>~ /wbuart32/trunk/bench/cpp/helloworld.cpp<br />~ /wbuart32/trunk/bench/cpp/linetest.cpp<br />~ /wbuart32/trunk/bench/cpp/Makefile<br />~ /wbuart32/trunk/bench/cpp/speech.txt<br />~ /wbuart32/trunk/bench/cpp/speechtest.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.h<br />~ /wbuart32/trunk/bench/verilog/linetest.v<br />~ /wbuart32/trunk/bench/verilog/Makefile<br />~ /wbuart32/trunk/bench/verilog/speechfifo.v<br />~ /wbuart32/trunk/doc/gpl-3.0.pdf<br />~ /wbuart32/trunk/doc/spec.pdf<br />~ /wbuart32/trunk/doc/src/spec.tex<br />~ /wbuart32/trunk/rtl/Makefile<br />~ /wbuart32/trunk/rtl/rxuart.v<br />~ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuartlite.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br /> dgisselq Wed, 15 Nov 2017 23:49:50 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=18 Biggest change: default_nettype Also fixed potential ufifo overload condition, and wbuart ... https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=17 <div><strong>Rev 17 - dgisselq</strong> (6 file(s) modified)</div><div>Biggest change: default_nettype<br /> <br /> Also fixed potential ufifo overload condition, and wbuart ...</div>~ /wbuart32/trunk/rtl/rxuart.v<br />~ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />~ /wbuart32/trunk/rtl/txuartlite.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br /> dgisselq Fri, 21 Apr 2017 21:21:40 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=17 Updated the property list for cpp directory. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=16 <div><strong>Rev 16 - dgisselq</strong> (1 file(s) modified)</div><div>Updated the property list for cpp directory.</div>~ /wbuart32/trunk/bench/cpp<br /> dgisselq Tue, 28 Mar 2017 16:40:07 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=16 Added a set of lite-UARTs that only handle 8N1 to ... https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=15 <div><strong>Rev 15 - dgisselq</strong> (20 file(s) modified)</div><div>Added a set of lite-UARTs that only handle 8N1 to ...</div>~ /wbuart32/trunk<br />~ /wbuart32/trunk/bench/cpp<br />~ /wbuart32/trunk/bench/cpp/linetest.cpp<br />~ /wbuart32/trunk/bench/verilog<br />~ /wbuart32/trunk/bench/verilog/echotest.v<br />~ /wbuart32/trunk/bench/verilog/helloworld.v<br />~ /wbuart32/trunk/bench/verilog/linetest.v<br />~ /wbuart32/trunk/bench/verilog/Makefile<br />~ /wbuart32/trunk/bench/verilog/speechfifo.v<br />~ /wbuart32/trunk/doc/spec.pdf<br />~ /wbuart32/trunk/doc/src/spec.tex<br />~ /wbuart32/trunk/README.md<br />~ /wbuart32/trunk/rtl<br />~ /wbuart32/trunk/rtl/Makefile<br />+ /wbuart32/trunk/rtl/rxuartlite.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />+ /wbuart32/trunk/rtl/txuartlite.v<br />~ /wbuart32/trunk/rtl/wbuart-insert.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br />~ /wbuart32/trunk/wbuart32.core<br /> dgisselq Tue, 28 Mar 2017 16:39:20 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=15 This version works on hardware. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=14 <div><strong>Rev 14 - dgisselq</strong> (3 file(s) modified)</div><div>This version works on hardware.</div>~ /wbuart32/trunk/rtl/rxuart.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br /> dgisselq Tue, 21 Feb 2017 14:25:45 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=14 Adjusted documentation of OPT_STANDALONE, and updated internal README files. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=13 <div><strong>Rev 13 - dgisselq</strong> (7 file(s) modified)</div><div>Adjusted documentation of OPT_STANDALONE, and updated internal README files.</div>~ /wbuart32/trunk/bench/README.md<br />~ /wbuart32/trunk/bench/verilog/echotest.v<br />~ /wbuart32/trunk/bench/verilog/helloworld.v<br />~ /wbuart32/trunk/bench/verilog/linetest.v<br />~ /wbuart32/trunk/bench/verilog/README.md<br />~ /wbuart32/trunk/doc/gpl-3.0.pdf<br />~ /wbuart32/trunk/README.md<br /> dgisselq Mon, 20 Feb 2017 18:19:55 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=13 Added hardware flow control information to the specification. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=12 <div><strong>Rev 12 - dgisselq</strong> (2 file(s) modified)</div><div>Added hardware flow control information to the specification.</div>~ /wbuart32/trunk/doc/spec.pdf<br />~ /wbuart32/trunk/doc/src/spec.tex<br /> dgisselq Mon, 20 Feb 2017 17:59:54 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=12 Modified mkspeech to create both hex and include files, to ... https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=11 <div><strong>Rev 11 - dgisselq</strong> (4 file(s) modified)</div><div>Modified mkspeech to create both hex and include files, to ...</div>~ /wbuart32/trunk/bench/cpp/Makefile<br />~ /wbuart32/trunk/bench/cpp/mkspeech.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.cpp<br />~ /wbuart32/trunk/bench/cpp/uartsim.h<br /> dgisselq Mon, 20 Feb 2017 17:57:56 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=11 Adjusted for the new hardware flow control capability. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=10 <div><strong>Rev 10 - dgisselq</strong> (4 file(s) modified)</div><div>Adjusted for the new hardware flow control capability.</div>~ /wbuart32/trunk/bench/verilog/echotest.v<br />~ /wbuart32/trunk/bench/verilog/helloworld.v<br />~ /wbuart32/trunk/bench/verilog/linetest.v<br />~ /wbuart32/trunk/bench/verilog/speechfifo.v<br /> dgisselq Mon, 20 Feb 2017 17:53:37 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=10 Added a hardware flow control capability. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=9 <div><strong>Rev 9 - dgisselq</strong> (5 file(s) modified)</div><div>Added a hardware flow control capability.</div>~ /wbuart32/trunk/rtl/rxuart.v<br />~ /wbuart32/trunk/rtl/txuart.v<br />~ /wbuart32/trunk/rtl/ufifo.v<br />~ /wbuart32/trunk/rtl/wbuart-insert.v<br />~ /wbuart32/trunk/rtl/wbuart.v<br /> dgisselq Mon, 20 Feb 2017 17:50:50 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=9 Updated the documents to reference the new testbenches. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=8 <div><strong>Rev 8 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the documents to reference the new testbenches.</div>~ /wbuart32/trunk/doc/gpl-3.0.pdf<br />~ /wbuart32/trunk/doc/spec.pdf<br /> dgisselq Fri, 20 Jan 2017 14:56:33 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=8 Moved the definition of state to before its first usage. https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=7 <div><strong>Rev 7 - dgisselq</strong> (1 file(s) modified)</div><div>Moved the definition of state to before its first usage.</div>~ /wbuart32/trunk/rtl/rxuart.v<br /> dgisselq Fri, 20 Jan 2017 14:55:57 +0100 https://opencores.org/websvn//websvn/revision?repname=wbuart32&path=%2Fwbuart32%2F&rev=7
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