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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2F&
Fri, 15 May 2026 16:25:26 +0100FeedCreator 1.7.2Cleaned up the stall logic--made it independent of whether or ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180
<div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />dgisselqThu, 15 Sep 2016 20:20:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180Lots of changes, most (all?) of them to the non-pipelined ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179
<div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqThu, 15 Sep 2016 20:18:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179Rewrote the parameter controlled logic to be just that: perameter ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178
<div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqThu, 15 Sep 2016 20:17:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178Fixed the illegal address logic to be more precise.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=177
<div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />dgisselqThu, 15 Sep 2016 20:14:26 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=177Switched from distributed to block RAM, and adjusted the logic ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=176
<div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqThu, 15 Sep 2016 20:13:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=176Fixed the carry bit for logical shifts: it is the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=175
<div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqThu, 15 Sep 2016 20:10:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=175Simplified the divide to improve timing performance.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=174
<div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 15 Sep 2016 20:06:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=174Adjusted the pdfinfo field, to accommodate Google's bot.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=173
<div><strong>Rev 173 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the pdfinfo field, to accommodate Google's bot.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 15 Sep 2016 20:03:34 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=173Added a test to see if the compiler properly handles ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=172
<div><strong>Rev 172 - dgisselq</strong> (1 file(s) modified)</div><div>Added a test to see if the compiler properly handles ...</div>~ /zipcpu/trunk/bench/asm/cputest.c<br />dgisselqThu, 15 Sep 2016 20:02:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=172This fixes the problem whereby the ZipCPU didn't properly access ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=171
<div><strong>Rev 171 - dgisselq</strong> (2 file(s) modified)</div><div>This fixes the problem whereby the ZipCPU didn't properly access ...</div>~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />dgisselqTue, 13 Sep 2016 14:40:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=171Minor updates to the orconf.pdf pre-conference slide. (Added the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=170
<div><strong>Rev 170 - dgisselq</strong> (1 file(s) modified)</div><div>Minor updates to the orconf.pdf pre-conference slide. (Added the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqSat, 03 Sep 2016 20:32:47 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=170Added details of LM32 to the (pre) ORConf survey slide ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=169
<div><strong>Rev 169 - dgisselq</strong> (1 file(s) modified)</div><div>Added details of LM32 to the (pre) ORConf survey slide ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqFri, 29 Jul 2016 20:19:08 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=169An updated version of the intensive CPU test. This ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=168
<div><strong>Rev 168 - dgisselq</strong> (1 file(s) modified)</div><div>An updated version of the intensive CPU test. This ...</div>+ /zipcpu/trunk/bench/asm/cputest.c<br />dgisselqSat, 16 Jul 2016 20:26:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=168Updated the spec to reflect changes in the CC register: ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=167
<div><strong>Rev 167 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the spec to reflect changes in the CC register: ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqSat, 16 Jul 2016 20:25:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=167Bugfix version. This fixes a problem whereby function addresses ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=166
<div><strong>Rev 166 - dgisselq</strong> (1 file(s) modified)</div><div>Bugfix version. This fixes a problem whereby function addresses ...</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />dgisselqSat, 16 Jul 2016 16:22:15 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=166Added a test to make certain that the arithmetic right ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=165
<div><strong>Rev 165 - dgisselq</strong> (1 file(s) modified)</div><div>Added a test to make certain that the arithmetic right ...</div>~ /zipcpu/trunk/sw/zasm/test.S<br />dgisselqSat, 16 Jul 2016 16:21:04 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=165Updated with inputs from Hellwig Geisse regarding the details of ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=164
<div><strong>Rev 164 - dgisselq</strong> (1 file(s) modified)</div><div>Updated with inputs from Hellwig Geisse regarding the details of ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqFri, 08 Jul 2016 14:38:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=164Trimmed OR1K instruction set down from 219 instructions, to the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=163
<div><strong>Rev 163 - dgisselq</strong> (1 file(s) modified)</div><div>Trimmed OR1K instruction set down from 219 instructions, to the ...</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 12:39:16 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=163Noted 64-bit integers are by extension, as are vector instructions.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=162
<div><strong>Rev 162 - dgisselq</strong> (1 file(s) modified)</div><div>Noted 64-bit integers are by extension, as are vector instructions.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 11:58:27 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=162Initial version of the ORConf slides, showing only the initial ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=161
<div><strong>Rev 161 - dgisselq</strong> (1 file(s) modified)</div><div>Initial version of the ORConf slides, showing only the initial ...</div>+ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 30 Jun 2016 11:50:03 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=161
