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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2F&
Fri, 12 Jun 2026 09:03:21 +0100FeedCreator 1.7.2Added the copyright statement back in.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190
<div><strong>Rev 190 - dgisselq</strong> (1 file(s) modified)</div><div>Added the copyright statement back in.</div>~ /zipcpu/trunk/doc/Makefile<br />dgisselqMon, 17 Oct 2016 23:21:09 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190Final, as delivered, ORCONF slides.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189
<div><strong>Rev 189 - dgisselq</strong> (1 file(s) modified)</div><div>Final, as delivered, ORCONF slides.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqMon, 17 Oct 2016 23:19:44 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189Adjusted the opcodes to match the binutils port: added RTN ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188
<div><strong>Rev 188 - dgisselq</strong> (2 file(s) modified)</div><div>Adjusted the opcodes to match the binutils port: added RTN ...</div>~ /zipcpu/trunk/sw/zasm/obj-pc/depends.txt<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />dgisselqThu, 15 Sep 2016 21:02:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188Updated to match changed register definitions within the core.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=187
<div><strong>Rev 187 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to match changed register definitions within the core.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />dgisselqThu, 15 Sep 2016 20:31:52 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=187Now allows profile dumping for ELF executables.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=186
<div><strong>Rev 186 - dgisselq</strong> (1 file(s) modified)</div><div>Now allows profile dumping for ELF executables.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />dgisselqThu, 15 Sep 2016 20:31:19 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=186Now includes the proper flags for building with ELF executable ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=185
<div><strong>Rev 185 - dgisselq</strong> (1 file(s) modified)</div><div>Now includes the proper flags for building with ELF executable ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />dgisselqThu, 15 Sep 2016 20:30:29 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=185Adjusted the illegal instruction option documentation.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=184
<div><strong>Rev 184 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the illegal instruction option documentation.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />dgisselqThu, 15 Sep 2016 20:24:56 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=184Cleaned up the system so that !CYC implies !STB as ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=183
<div><strong>Rev 183 - dgisselq</strong> (2 file(s) modified)</div><div>Cleaned up the system so that !CYC implies !STB as ...</div>~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 15 Sep 2016 20:24:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=183Bug fix for fast memories. This now works for ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=182
<div><strong>Rev 182 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix for fast memories. This now works for ...</div>~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />dgisselqThu, 15 Sep 2016 20:23:00 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=182Adjusted the wishbone logic to include our wishbone simplification that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=181
<div><strong>Rev 181 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the wishbone logic to include our wishbone simplification that ...</div>~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />dgisselqThu, 15 Sep 2016 20:21:22 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=181Cleaned up the stall logic--made it independent of whether or ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180
<div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />dgisselqThu, 15 Sep 2016 20:20:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180Lots of changes, most (all?) of them to the non-pipelined ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179
<div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqThu, 15 Sep 2016 20:18:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179Rewrote the parameter controlled logic to be just that: perameter ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178
<div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqThu, 15 Sep 2016 20:17:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178Fixed the illegal address logic to be more precise.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=177
<div><strong>Rev 177 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the illegal address logic to be more precise.</div>~ /zipcpu/trunk/rtl/core/pipefetch.v<br />dgisselqThu, 15 Sep 2016 20:14:26 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=177Switched from distributed to block RAM, and adjusted the logic ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=176
<div><strong>Rev 176 - dgisselq</strong> (1 file(s) modified)</div><div>Switched from distributed to block RAM, and adjusted the logic ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqThu, 15 Sep 2016 20:13:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=176Fixed the carry bit for logical shifts: it is the ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=175
<div><strong>Rev 175 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the carry bit for logical shifts: it is the ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqThu, 15 Sep 2016 20:10:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=175Simplified the divide to improve timing performance.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=174
<div><strong>Rev 174 - dgisselq</strong> (1 file(s) modified)</div><div>Simplified the divide to improve timing performance.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 15 Sep 2016 20:06:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=174Adjusted the pdfinfo field, to accommodate Google's bot.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=173
<div><strong>Rev 173 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the pdfinfo field, to accommodate Google's bot.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqThu, 15 Sep 2016 20:03:34 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=173Added a test to see if the compiler properly handles ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=172
<div><strong>Rev 172 - dgisselq</strong> (1 file(s) modified)</div><div>Added a test to see if the compiler properly handles ...</div>~ /zipcpu/trunk/bench/asm/cputest.c<br />dgisselqThu, 15 Sep 2016 20:02:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=172This fixes the problem whereby the ZipCPU didn't properly access ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=171
<div><strong>Rev 171 - dgisselq</strong> (2 file(s) modified)</div><div>This fixes the problem whereby the ZipCPU didn't properly access ...</div>~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />dgisselqTue, 13 Sep 2016 14:40:35 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=171
