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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2F&
Fri, 12 Jun 2026 20:06:38 +0100FeedCreator 1.7.2Added a new multiply testbench. Other changes were necessary ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=197
<div><strong>Rev 197 - dgisselq</strong> (5 file(s) modified)</div><div>Added a new multiply testbench. Other changes were necessary ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />+ /zipcpu/trunk/bench/cpp/mpy_tb.cpp<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />dgisselqThu, 03 Nov 2016 18:22:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=197Updated internal documentation.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=196
<div><strong>Rev 196 - dgisselq</strong> (1 file(s) modified)</div><div>Updated internal documentation.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqThu, 03 Nov 2016 18:21:53 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=196Adds a new mode that can handle a delayed stall ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=195
<div><strong>Rev 195 - dgisselq</strong> (1 file(s) modified)</div><div>Adds a new mode that can handle a delayed stall ...</div>~ /zipcpu/trunk/rtl/aux/busdelay.v<br />dgisselqThu, 03 Nov 2016 18:21:30 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=195Cleaned up some parameters, trying to create more consistency.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=194
<div><strong>Rev 194 - dgisselq</strong> (3 file(s) modified)</div><div>Cleaned up some parameters, trying to create more consistency.</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 03 Nov 2016 18:20:42 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=194These changes make it so the ALU multiplies pass a ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=193
<div><strong>Rev 193 - dgisselq</strong> (4 file(s) modified)</div><div>These changes make it so the ALU multiplies pass a ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />dgisselqThu, 03 Nov 2016 18:19:37 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=193Fixed a bug with constant alignment in the assembler.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=192
<div><strong>Rev 192 - dgisselq</strong> (3 file(s) modified)</div><div>Fixed a bug with constant alignment in the assembler.</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />dgisselqThu, 03 Nov 2016 18:18:40 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=192Updated toolchain, more information on the example debugger.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=191
<div><strong>Rev 191 - dgisselq</strong> (6 file(s) modified)</div><div>Updated toolchain, more information on the example debugger.</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/README<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />dgisselqWed, 19 Oct 2016 15:12:27 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=191Added the copyright statement back in.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190
<div><strong>Rev 190 - dgisselq</strong> (1 file(s) modified)</div><div>Added the copyright statement back in.</div>~ /zipcpu/trunk/doc/Makefile<br />dgisselqMon, 17 Oct 2016 23:21:09 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190Final, as delivered, ORCONF slides.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189
<div><strong>Rev 189 - dgisselq</strong> (1 file(s) modified)</div><div>Final, as delivered, ORCONF slides.</div>~ /zipcpu/trunk/doc/orconf.pdf<br />dgisselqMon, 17 Oct 2016 23:19:44 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189Adjusted the opcodes to match the binutils port: added RTN ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188
<div><strong>Rev 188 - dgisselq</strong> (2 file(s) modified)</div><div>Adjusted the opcodes to match the binutils port: added RTN ...</div>~ /zipcpu/trunk/sw/zasm/obj-pc/depends.txt<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />dgisselqThu, 15 Sep 2016 21:02:17 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188Updated to match changed register definitions within the core.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=187
<div><strong>Rev 187 - dgisselq</strong> (1 file(s) modified)</div><div>Updated to match changed register definitions within the core.</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />dgisselqThu, 15 Sep 2016 20:31:52 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=187Now allows profile dumping for ELF executables.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=186
<div><strong>Rev 186 - dgisselq</strong> (1 file(s) modified)</div><div>Now allows profile dumping for ELF executables.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />dgisselqThu, 15 Sep 2016 20:31:19 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=186Now includes the proper flags for building with ELF executable ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=185
<div><strong>Rev 185 - dgisselq</strong> (1 file(s) modified)</div><div>Now includes the proper flags for building with ELF executable ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />dgisselqThu, 15 Sep 2016 20:30:29 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=185Adjusted the illegal instruction option documentation.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=184
<div><strong>Rev 184 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the illegal instruction option documentation.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />dgisselqThu, 15 Sep 2016 20:24:56 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=184Cleaned up the system so that !CYC implies !STB as ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=183
<div><strong>Rev 183 - dgisselq</strong> (2 file(s) modified)</div><div>Cleaned up the system so that !CYC implies !STB as ...</div>~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqThu, 15 Sep 2016 20:24:05 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=183Bug fix for fast memories. This now works for ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=182
<div><strong>Rev 182 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix for fast memories. This now works for ...</div>~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />dgisselqThu, 15 Sep 2016 20:23:00 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=182Adjusted the wishbone logic to include our wishbone simplification that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=181
<div><strong>Rev 181 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the wishbone logic to include our wishbone simplification that ...</div>~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />dgisselqThu, 15 Sep 2016 20:21:22 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=181Cleaned up the stall logic--made it independent of whether or ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180
<div><strong>Rev 180 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the stall logic--made it independent of whether or ...</div>~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />dgisselqThu, 15 Sep 2016 20:20:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=180Lots of changes, most (all?) of them to the non-pipelined ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179
<div><strong>Rev 179 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of changes, most (all?) of them to the non-pipelined ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqThu, 15 Sep 2016 20:18:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=179Rewrote the parameter controlled logic to be just that: perameter ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178
<div><strong>Rev 178 - dgisselq</strong> (1 file(s) modified)</div><div>Rewrote the parameter controlled logic to be just that: perameter ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br />dgisselqThu, 15 Sep 2016 20:17:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=178
