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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2F& Sat, 29 Jan 2022 13:15:12 +0100 FeedCreator 1.7.2 Updated the ELF support, and divide test-bench. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=207 <div><strong>Rev 207 - dgisselq</strong> (2 file(s) modified)</div><div>Updated the ELF support, and divide test-bench.</div>~ /zipcpu/trunk/sim/cpp/zipelf.cpp<br />~ /zipcpu/trunk/sim/verilator/div_tb.cpp<br /> dgisselq Tue, 28 Mar 2017 15:28:57 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=207 Updated assembler, fixes several bugs, adds better bug detection and ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=206 <div><strong>Rev 206 - dgisselq</strong> (2 file(s) modified)</div><div>Updated assembler, fixes several bugs, adds better bug detection and ...</div>~ /zipcpu/trunk/sw/gas-script.sh<br />~ /zipcpu/trunk/sw/gas-zippatch.patch<br /> dgisselq Tue, 28 Mar 2017 15:28:15 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=206 Updating core to current/best version, to include dblfetch support and ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=205 <div><strong>Rev 205 - dgisselq</strong> (8 file(s) modified)</div><div>Updating core to current/best version, to include dblfetch support and ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/dblfetch.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br /> dgisselq Tue, 28 Mar 2017 15:26:49 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=205 Added the two simulators back into the SVN repository https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=204 <div><strong>Rev 204 - dgisselq</strong> (29 file(s) modified)</div><div>Added the two simulators back into the SVN repository</div>+ /zipcpu/trunk/bench/cpp/helloworld.c<br />+ /zipcpu/trunk/bench/zipsim.ld<br />+ /zipcpu/trunk/sim<br />+ /zipcpu/trunk/sim/cpp<br />+ /zipcpu/trunk/sim/cpp/Makefile<br />+ /zipcpu/trunk/sim/cpp/twoc.cpp<br />+ /zipcpu/trunk/sim/cpp/twoc.h<br />+ /zipcpu/trunk/sim/cpp/zipelf.cpp<br />+ /zipcpu/trunk/sim/cpp/zipelf.h<br />+ /zipcpu/trunk/sim/cpp/zsim.cpp<br />+ /zipcpu/trunk/sim/verilator<br />+ /zipcpu/trunk/sim/verilator/.gitignore<br />+ /zipcpu/trunk/sim/verilator/byteswap.cpp<br />+ /zipcpu/trunk/sim/verilator/byteswap.h<br />+ /zipcpu/trunk/sim/verilator/div_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/Makefile<br />+ /zipcpu/trunk/sim/verilator/memsim.cpp<br />+ /zipcpu/trunk/sim/verilator/memsim.h<br />+ /zipcpu/trunk/sim/verilator/mpy_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/pdump.cpp<br />+ /zipcpu/trunk/sim/verilator/pfcache_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/testb.h<br />+ /zipcpu/trunk/sim/verilator/twoc.cpp<br />+ /zipcpu/trunk/sim/verilator/twoc.h<br />+ /zipcpu/trunk/sim/verilator/zipelf.cpp<br />+ /zipcpu/trunk/sim/verilator/zipelf.h<br />+ /zipcpu/trunk/sim/verilator/zipmmu_tb.cpp<br />+ /zipcpu/trunk/sim/verilator/zippy_tb.cpp<br />+ /zipcpu/trunk/sim/zip-sim.exp<br /> dgisselq Thu, 09 Mar 2017 20:08:46 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=204 Removed the (now unused) old GCC compiler, v5.3.0 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=203 <div><strong>Rev 203 - dgisselq</strong> (2 file(s) modified)</div><div>Removed the (now unused) old GCC compiler, v5.3.0</div>- /zipcpu/trunk/sw/gcc-5.3.0-specs-1.patch<br />- /zipcpu/trunk/sw/gcc-5.3.0.tar.bz2<br /> dgisselq Thu, 09 Mar 2017 20:07:20 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=203 Additional ZipCPU changes associated w 8b upgrade https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=202 <div><strong>Rev 202 - dgisselq</strong> (38 file(s) modified)</div><div>Additional ZipCPU changes associated w 8b upgrade</div>~ /zipcpu/trunk/bench/asm/cputest.c<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/doc/gfx<br />+ /zipcpu/trunk/doc/gfx/bus-structure.eps<br />+ /zipcpu/trunk/doc/gfx/bus-structure.png<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />+ /zipcpu/trunk/doc/gfx/zipbones.eps<br />- /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />+ /zipcpu/trunk/doc/memsurvey.png<br />+ /zipcpu/trunk/doc/nextgen.html<br />+ /zipcpu/trunk/doc/nextgen.png<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/sw<br />+ /zipcpu/trunk/sw/.gitignore<br />- /zipcpu/trunk/sw/binutils-2.25.patch<br />- /zipcpu/trunk/sw/binutils-2.25.tar.bz2<br />+ /zipcpu/trunk/sw/binutils-2.27.tar.bz2<br />~ /zipcpu/trunk/sw/gas-script.sh<br />+ /zipcpu/trunk/sw/gas-zippatch.patch<br />+ /zipcpu/trunk/sw/gcc-6.2.0.tar.bz2<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br />+ /zipcpu/trunk/sw/newlib-2.5.0.tar.gz<br />+ /zipcpu/trunk/sw/nlib-script.sh<br />+ /zipcpu/trunk/sw/nlib-zippatch.patch<br />~ /zipcpu/trunk/sw/zasm<br />+ /zipcpu/trunk/sw/zasm/.gitignore<br />- /zipcpu/trunk/sw/zasm/obj-pc<br />+ /zipcpu/trunk/sw/zasm/README.md<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/zip.vim<br /> dgisselq Thu, 09 Mar 2017 19:13:56 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=202 RTL files for the 8-bit capable ZipCPU. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=201 <div><strong>Rev 201 - dgisselq</strong> (30 file(s) modified)</div><div>RTL files for the 8-bit capable ZipCPU.</div>~ /zipcpu/trunk/rtl<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />- /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/dcache.v<br />~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />- /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />~ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />+ /zipcpu/trunk/rtl/peripherals/zipmmu.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 09 Mar 2017 18:08:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=201 Lots of GCC bugs fixed, some new features added, longs ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=200 <div><strong>Rev 200 - dgisselq</strong> (5 file(s) modified)</div><div>Lots of GCC bugs fixed, some new features added, longs ...</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gas-script.sh<br />~ /zipcpu/trunk/sw/gcc-script.sh<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/zasm/Makefile<br /> dgisselq Wed, 30 Nov 2016 11:32:41 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=200 Massive specification rewrite, brings it up to date with the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=199 <div><strong>Rev 199 - dgisselq</strong> (2 file(s) modified)</div><div>Massive specification rewrite, brings it up to date with the ...</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Fri, 04 Nov 2016 22:53:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=199 Added a copyright notice. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=198 <div><strong>Rev 198 - dgisselq</strong> (1 file(s) modified)</div><div>Added a copyright notice.</div>~ /zipcpu/trunk/zip.vim<br /> dgisselq Thu, 03 Nov 2016 18:23:41 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=198 Added a new multiply testbench. Other changes were necessary ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=197 <div><strong>Rev 197 - dgisselq</strong> (5 file(s) modified)</div><div>Added a new multiply testbench. Other changes were necessary ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />+ /zipcpu/trunk/bench/cpp/mpy_tb.cpp<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Thu, 03 Nov 2016 18:22:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=197 Updated internal documentation. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=196 <div><strong>Rev 196 - dgisselq</strong> (1 file(s) modified)</div><div>Updated internal documentation.</div>~ /zipcpu/trunk/rtl/core/div.v<br /> dgisselq Thu, 03 Nov 2016 18:21:53 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=196 Adds a new mode that can handle a delayed stall ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=195 <div><strong>Rev 195 - dgisselq</strong> (1 file(s) modified)</div><div>Adds a new mode that can handle a delayed stall ...</div>~ /zipcpu/trunk/rtl/aux/busdelay.v<br /> dgisselq Thu, 03 Nov 2016 18:21:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=195 Cleaned up some parameters, trying to create more consistency. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=194 <div><strong>Rev 194 - dgisselq</strong> (3 file(s) modified)</div><div>Cleaned up some parameters, trying to create more consistency.</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 03 Nov 2016 18:20:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=194 These changes make it so the ALU multiplies pass a ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=193 <div><strong>Rev 193 - dgisselq</strong> (4 file(s) modified)</div><div>These changes make it so the ALU multiplies pass a ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br /> dgisselq Thu, 03 Nov 2016 18:19:37 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=193 Fixed a bug with constant alignment in the assembler. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=192 <div><strong>Rev 192 - dgisselq</strong> (3 file(s) modified)</div><div>Fixed a bug with constant alignment in the assembler.</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/Makefile<br /> dgisselq Thu, 03 Nov 2016 18:18:40 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=192 Updated toolchain, more information on the example debugger. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=191 <div><strong>Rev 191 - dgisselq</strong> (6 file(s) modified)</div><div>Updated toolchain, more information on the example debugger.</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />~ /zipcpu/trunk/sw/gcc-zippatch.patch<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/README<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br /> dgisselq Wed, 19 Oct 2016 15:12:27 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=191 Added the copyright statement back in. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190 <div><strong>Rev 190 - dgisselq</strong> (1 file(s) modified)</div><div>Added the copyright statement back in.</div>~ /zipcpu/trunk/doc/Makefile<br /> dgisselq Mon, 17 Oct 2016 23:21:09 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=190 Final, as delivered, ORCONF slides. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189 <div><strong>Rev 189 - dgisselq</strong> (1 file(s) modified)</div><div>Final, as delivered, ORCONF slides.</div>~ /zipcpu/trunk/doc/orconf.pdf<br /> dgisselq Mon, 17 Oct 2016 23:19:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=189 Adjusted the opcodes to match the binutils port: added RTN ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188 <div><strong>Rev 188 - dgisselq</strong> (2 file(s) modified)</div><div>Adjusted the opcodes to match the binutils port: added RTN ...</div>~ /zipcpu/trunk/sw/zasm/obj-pc/depends.txt<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br /> dgisselq Thu, 15 Sep 2016 21:02:17 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=188
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