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https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2F&
Thu, 28 Mar 2024 19:53:18 +0100FeedCreator 1.7.2Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=89
<div><strong>Rev 89 - dgisselq</strong> (4 file(s) modified)</div><div>Minor changes, to include making default branching an ADD.[condition] X,PC<br />
instruction, ...</div>~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />dgisselqThu, 28 Jan 2016 22:04:07 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=89Eliminated some warnings. The div fixes were to simplify ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=88
<div><strong>Rev 88 - dgisselq</strong> (3 file(s) modified)</div><div>Eliminated some warnings. The div fixes were to simplify ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />dgisselqMon, 04 Jan 2016 22:26:48 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=88Adjusted the operator input line to reflect actual logic inputs, ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=87
<div><strong>Rev 87 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the operator input line to reflect actual logic inputs, ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />dgisselqSat, 02 Jan 2016 23:56:30 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=87Removed the requirement to have the dev.scope.cpu hardware defined outside
of ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=86
<div><strong>Rev 86 - dgisselq</strong> (1 file(s) modified)</div><div>Removed the requirement to have the dev.scope.cpu hardware defined outside<br />
of ...</div>~ /zipcpu/trunk/bench/asm/zipdhry.S<br />dgisselqSat, 02 Jan 2016 23:55:01 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=86Minor update/correction to operand B definition.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=85
<div><strong>Rev 85 - dgisselq</strong> (1 file(s) modified)</div><div>Minor update/correction to operand B definition.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqSat, 02 Jan 2016 23:53:54 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=85Minor updates.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=84
<div><strong>Rev 84 - dgisselq</strong> (2 file(s) modified)</div><div>Minor updates.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqSat, 02 Jan 2016 23:52:25 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=84Added a flag to indicate whether an exception took place ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=83
<div><strong>Rev 83 - dgisselq</strong> (1 file(s) modified)</div><div>Added a flag to indicate whether an exception took place ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />dgisselqSat, 02 Jan 2016 23:51:37 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=83Found and (I hope) fixed a nasty bug that would ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=82
<div><strong>Rev 82 - dgisselq</strong> (1 file(s) modified)</div><div>Found and (I hope) fixed a nasty bug that would ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br />dgisselqSat, 02 Jan 2016 23:46:42 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=82Trying to clean up ISE generated warnings.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=81
<div><strong>Rev 81 - dgisselq</strong> (1 file(s) modified)</div><div>Trying to clean up ISE generated warnings.</div>~ /zipcpu/trunk/rtl/core/div.v<br />dgisselqSat, 02 Jan 2016 23:45:23 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=81Bug fix: declared the (combined) multiply to be signed again. ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=80
<div><strong>Rev 80 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix: declared the (combined) multiply to be signed again. ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />dgisselqSat, 02 Jan 2016 23:44:45 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=80Adjusted the opcodes for NOOP, BREAK, and LOCK.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=79
<div><strong>Rev 79 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the opcodes for NOOP, BREAK, and LOCK.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqTue, 29 Dec 2015 19:54:28 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=79Found/corrected annoying bug in floating point documentation of the opcode
table.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=78
<div><strong>Rev 78 - dgisselq</strong> (1 file(s) modified)</div><div>Found/corrected annoying bug in floating point documentation of the opcode<br />
table.</div>~ /zipcpu/trunk/doc/iset.html<br />dgisselqTue, 29 Dec 2015 19:53:25 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=78First check-in: the test bench for the divide instruction.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=77
<div><strong>Rev 77 - dgisselq</strong> (1 file(s) modified)</div><div>First check-in: the test bench for the divide instruction.</div>+ /zipcpu/trunk/bench/cpp/div_tb.cpp<br />dgisselqMon, 28 Dec 2015 20:53:32 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=77The biggest change here was to zippy_tb, to make it ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=76
<div><strong>Rev 76 - dgisselq</strong> (2 file(s) modified)</div><div>The biggest change here was to zippy_tb, to make it ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />dgisselqMon, 28 Dec 2015 20:50:30 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=76Modified for VLIW instructions.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=75
<div><strong>Rev 75 - dgisselq</strong> (1 file(s) modified)</div><div>Modified for VLIW instructions.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />dgisselqMon, 28 Dec 2015 20:49:16 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=75Added a bunch of debugging code to the Dhrystone benchmark ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=74
<div><strong>Rev 74 - dgisselq</strong> (4 file(s) modified)</div><div>Added a bunch of debugging code to the Dhrystone benchmark ...</div>~ /zipcpu/trunk/bench/asm/Makefile<br />+ /zipcpu/trunk/bench/asm/nullpc.s<br />+ /zipcpu/trunk/bench/asm/poptest.s<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />dgisselqMon, 28 Dec 2015 20:48:36 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=74Documentations updates.
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=73
<div><strong>Rev 73 - dgisselq</strong> (3 file(s) modified)</div><div>Documentations updates.</div>~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />dgisselqMon, 28 Dec 2015 20:39:21 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=73Some updated graphics, now containing images of the CPU that ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=72
<div><strong>Rev 72 - dgisselq</strong> (4 file(s) modified)</div><div>Some updated graphics, now containing images of the CPU that ...</div>~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />dgisselqMon, 28 Dec 2015 20:38:13 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=72This contains a bunch of bug fixes. (A lot ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=71
<div><strong>Rev 71 - dgisselq</strong> (7 file(s) modified)</div><div>This contains a bunch of bug fixes. (A lot ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />dgisselqMon, 28 Dec 2015 20:34:13 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=71Updated the assembler support files, zopcodes in particular, to handle ...
https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=70
<div><strong>Rev 70 - dgisselq</strong> (4 file(s) modified)</div><div>Updated the assembler support files, zopcodes in particular, to handle ...</div>~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />dgisselqMon, 28 Dec 2015 20:22:27 +0100https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2F&rev=70