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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F& Tue, 27 Sep 2022 12:14:51 +0100 FeedCreator 1.7.2 Adjusted the &quot;BREAK&quot; instruction so that it will now disassemble ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=101 <div><strong>Rev 101 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the &quot;BREAK&quot; instruction so that it will now disassemble ...</div>~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br /> dgisselq Thu, 03 Mar 2016 23:23:03 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=101 Some changes to support early branching: branches are now ADD ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=100 <div><strong>Rev 100 - dgisselq</strong> (1 file(s) modified)</div><div>Some changes to support early branching: branches are now ADD ...</div>~ /zipcpu/trunk/sw/zasm/zparser.h<br /> dgisselq Thu, 03 Mar 2016 23:21:19 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=100 Added big-endian versus little-endian functionality. You can now specify ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=99 <div><strong>Rev 99 - dgisselq</strong> (1 file(s) modified)</div><div>Added big-endian versus little-endian functionality. You can now specify ...</div>~ /zipcpu/trunk/sw/zasm/zdump.cpp<br /> dgisselq Thu, 03 Mar 2016 23:18:50 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=99 Added justed longjump instructions from the previous (not used, broken) functionality ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=98 <div><strong>Rev 98 - dgisselq</strong> (1 file(s) modified)</div><div>Added justed longjump instructions from the previous (not used, broken)<br /> functionality ...</div>~ /zipcpu/trunk/sw/zasm/zasm.l<br /> dgisselq Thu, 03 Mar 2016 23:17:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=98 Added longjump instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=97 <div><strong>Rev 97 - dgisselq</strong> (1 file(s) modified)</div><div>Added longjump instructions.</div>~ /zipcpu/trunk/sw/zasm/asmdata.h<br /> dgisselq Thu, 03 Mar 2016 23:16:46 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=97 Added the longjump functionality, so that the assembler will properly ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=96 <div><strong>Rev 96 - dgisselq</strong> (1 file(s) modified)</div><div>Added the longjump functionality, so that the assembler will properly ...</div>~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br /> dgisselq Thu, 03 Mar 2016 23:16:20 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=96 Fixed a bug whereby a mistaken code for CLR was ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=95 <div><strong>Rev 95 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed a bug whereby a mistaken code for CLR was ...</div>~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br /> dgisselq Tue, 01 Mar 2016 17:07:34 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=95 These changes make it possible to build binutils-2.25/ here in ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=94 <div><strong>Rev 94 - dgisselq</strong> (3 file(s) modified)</div><div>These changes make it possible to build binutils-2.25/ here in ...</div>~ /zipcpu/trunk/sw/binutils-2.25.patch<br />+ /zipcpu/trunk/sw/gas-script.sh<br />+ /zipcpu/trunk/sw/Makefile<br /> dgisselq Fri, 05 Feb 2016 20:03:07 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=94 A BINUTILS BACKEND IS NOW AVAILABLE!!!! https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=93 <div><strong>Rev 93 - dgisselq</strong> (2 file(s) modified)</div><div>A BINUTILS BACKEND IS NOW AVAILABLE!!!!</div>+ /zipcpu/trunk/sw/binutils-2.25.patch<br />+ /zipcpu/trunk/sw/binutils-2.25.tar.bz2<br /> dgisselq Thu, 28 Jan 2016 22:16:47 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=93 Adjustments made to match the simplified early branching. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=92 <div><strong>Rev 92 - dgisselq</strong> (2 file(s) modified)</div><div>Adjustments made to match the simplified early branching.</div>~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Thu, 28 Jan 2016 22:10:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=92 Minor updates. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=91 <div><strong>Rev 91 - dgisselq</strong> (2 file(s) modified)</div><div>Minor updates.</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br /> dgisselq Thu, 28 Jan 2016 22:08:23 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=91 Removed MOV x(PC),PC from the list of possible early branching ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=90 <div><strong>Rev 90 - dgisselq</strong> (1 file(s) modified)</div><div>Removed MOV x(PC),PC from the list of possible early branching ...</div>~ /zipcpu/trunk/rtl/core/idecode.v<br /> dgisselq Thu, 28 Jan 2016 22:07:02 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=90 Minor changes, to include making default branching an ADD.[condition] X,PC instruction, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=89 <div><strong>Rev 89 - dgisselq</strong> (4 file(s) modified)</div><div>Minor changes, to include making default branching an ADD.[condition] X,PC<br /> instruction, ...</div>~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br /> dgisselq Thu, 28 Jan 2016 22:04:07 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=89 Eliminated some warnings. The div fixes were to simplify ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=88 <div><strong>Rev 88 - dgisselq</strong> (3 file(s) modified)</div><div>Eliminated some warnings. The div fixes were to simplify ...</div>~ /zipcpu/trunk/rtl/core/div.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br /> dgisselq Mon, 04 Jan 2016 22:26:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=88 Adjusted the operator input line to reflect actual logic inputs, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=87 <div><strong>Rev 87 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the operator input line to reflect actual logic inputs, ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Sat, 02 Jan 2016 23:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=87 Removed the requirement to have the dev.scope.cpu hardware defined outside of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=86 <div><strong>Rev 86 - dgisselq</strong> (1 file(s) modified)</div><div>Removed the requirement to have the dev.scope.cpu hardware defined outside<br /> of ...</div>~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Sat, 02 Jan 2016 23:55:01 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=86 Minor update/correction to operand B definition. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=85 <div><strong>Rev 85 - dgisselq</strong> (1 file(s) modified)</div><div>Minor update/correction to operand B definition.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Sat, 02 Jan 2016 23:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=85 Minor updates. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=84 <div><strong>Rev 84 - dgisselq</strong> (2 file(s) modified)</div><div>Minor updates.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Sat, 02 Jan 2016 23:52:25 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=84 Added a flag to indicate whether an exception took place ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=83 <div><strong>Rev 83 - dgisselq</strong> (1 file(s) modified)</div><div>Added a flag to indicate whether an exception took place ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Sat, 02 Jan 2016 23:51:37 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=83 Found and (I hope) fixed a nasty bug that would ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=82 <div><strong>Rev 82 - dgisselq</strong> (1 file(s) modified)</div><div>Found and (I hope) fixed a nasty bug that would ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br /> dgisselq Sat, 02 Jan 2016 23:46:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=82
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