OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Error creating feed file, please check write permissions.
zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F& Wed, 15 Apr 2026 06:13:21 +0100 FeedCreator 1.7.2 Minor updates. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=84 <div><strong>Rev 84 - dgisselq</strong> (2 file(s) modified)</div><div>Minor updates.</div>~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Sat, 02 Jan 2016 23:52:25 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=84 Added a flag to indicate whether an exception took place ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=83 <div><strong>Rev 83 - dgisselq</strong> (1 file(s) modified)</div><div>Added a flag to indicate whether an exception took place ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Sat, 02 Jan 2016 23:51:37 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=83 Found and (I hope) fixed a nasty bug that would ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=82 <div><strong>Rev 82 - dgisselq</strong> (1 file(s) modified)</div><div>Found and (I hope) fixed a nasty bug that would ...</div>~ /zipcpu/trunk/rtl/core/pfcache.v<br /> dgisselq Sat, 02 Jan 2016 23:46:42 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=82 Trying to clean up ISE generated warnings. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=81 <div><strong>Rev 81 - dgisselq</strong> (1 file(s) modified)</div><div>Trying to clean up ISE generated warnings.</div>~ /zipcpu/trunk/rtl/core/div.v<br /> dgisselq Sat, 02 Jan 2016 23:45:23 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=81 Bug fix: declared the (combined) multiply to be signed again. ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=80 <div><strong>Rev 80 - dgisselq</strong> (1 file(s) modified)</div><div>Bug fix: declared the (combined) multiply to be signed again. ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br /> dgisselq Sat, 02 Jan 2016 23:44:45 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=80 Adjusted the opcodes for NOOP, BREAK, and LOCK. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=79 <div><strong>Rev 79 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the opcodes for NOOP, BREAK, and LOCK.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Tue, 29 Dec 2015 19:54:28 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=79 Found/corrected annoying bug in floating point documentation of the opcode table. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=78 <div><strong>Rev 78 - dgisselq</strong> (1 file(s) modified)</div><div>Found/corrected annoying bug in floating point documentation of the opcode<br /> table.</div>~ /zipcpu/trunk/doc/iset.html<br /> dgisselq Tue, 29 Dec 2015 19:53:25 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=78 First check-in: the test bench for the divide instruction. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=77 <div><strong>Rev 77 - dgisselq</strong> (1 file(s) modified)</div><div>First check-in: the test bench for the divide instruction.</div>+ /zipcpu/trunk/bench/cpp/div_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:53:32 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=77 The biggest change here was to zippy_tb, to make it ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=76 <div><strong>Rev 76 - dgisselq</strong> (2 file(s) modified)</div><div>The biggest change here was to zippy_tb, to make it ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:50:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=76 Modified for VLIW instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=75 <div><strong>Rev 75 - dgisselq</strong> (1 file(s) modified)</div><div>Modified for VLIW instructions.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br /> dgisselq Mon, 28 Dec 2015 20:49:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=75 Added a bunch of debugging code to the Dhrystone benchmark ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=74 <div><strong>Rev 74 - dgisselq</strong> (4 file(s) modified)</div><div>Added a bunch of debugging code to the Dhrystone benchmark ...</div>~ /zipcpu/trunk/bench/asm/Makefile<br />+ /zipcpu/trunk/bench/asm/nullpc.s<br />+ /zipcpu/trunk/bench/asm/poptest.s<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Mon, 28 Dec 2015 20:48:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=74 Documentations updates. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=73 <div><strong>Rev 73 - dgisselq</strong> (3 file(s) modified)</div><div>Documentations updates.</div>~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Mon, 28 Dec 2015 20:39:21 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=73 Some updated graphics, now containing images of the CPU that ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=72 <div><strong>Rev 72 - dgisselq</strong> (4 file(s) modified)</div><div>Some updated graphics, now containing images of the CPU that ...</div>~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br /> dgisselq Mon, 28 Dec 2015 20:38:13 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=72 This contains a bunch of bug fixes. (A lot ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=71 <div><strong>Rev 71 - dgisselq</strong> (7 file(s) modified)</div><div>This contains a bunch of bug fixes. (A lot ...</div>~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/rtl/core/idecode.v<br />~ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Mon, 28 Dec 2015 20:34:13 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=71 Updated the assembler support files, zopcodes in particular, to handle ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=70 <div><strong>Rev 70 - dgisselq</strong> (4 file(s) modified)</div><div>Updated the assembler support files, zopcodes in particular, to handle ...</div>~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br /> dgisselq Mon, 28 Dec 2015 20:22:27 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=70 This implements the &quot;new Instruction Set&quot; architecture for the Zip ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=69 <div><strong>Rev 69 - dgisselq</strong> (85 file(s) modified)</div><div>This implements the &quot;new Instruction Set&quot; architecture for the Zip ...</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/ivec.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/pcpc.S<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/twoc.cpp<br />~ /zipcpu/trunk/bench/cpp/twoc.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/gfx/bc.eps<br />~ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/memrd.eps<br />~ /zipcpu/trunk/doc/gfx/memwr.eps<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/div.v<br />+ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/lib/divs.S<br />~ /zipcpu/trunk/sw/lib/divu.S<br />~ /zipcpu/trunk/sw/lib/mpy32s.S<br />~ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/asmdata.h<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/twoc.cpp<br />~ /zipcpu/trunk/sw/zasm/twoc.h<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />+ /zipcpu/trunk/zip.vim<br /> dgisselq Tue, 22 Dec 2015 16:06:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=69 Updated specification, includes well illustrated pipeline discussion. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=68 <div><strong>Rev 68 - dgisselq</strong> (3 file(s) modified)</div><div>Updated specification, includes well illustrated pipeline discussion.</div>~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br /> dgisselq Tue, 17 Nov 2015 15:44:50 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=68 Includes timing diagrams in support of a very descriptive specification ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=67 <div><strong>Rev 67 - dgisselq</strong> (17 file(s) modified)</div><div>Includes timing diagrams in support of a very descriptive specification ...</div>+ /zipcpu/trunk/doc/gfx/bc.eps<br />+ /zipcpu/trunk/doc/gfx/bcmem.eps<br />+ /zipcpu/trunk/doc/gfx/bdbroken.eps<br />+ /zipcpu/trunk/doc/gfx/bdly.eps<br />+ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />+ /zipcpu/trunk/doc/gfx/fullpline.eps<br />+ /zipcpu/trunk/doc/gfx/memrd.eps<br />+ /zipcpu/trunk/doc/gfx/memwr.eps<br />+ /zipcpu/trunk/doc/gfx/sleep.eps<br />+ /zipcpu/trunk/doc/gfx/stacking.eps<br />+ /zipcpu/trunk/doc/gfx/stuttra.eps<br />+ /zipcpu/trunk/doc/gfx/stuttrb.eps<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br /> dgisselq Tue, 17 Nov 2015 15:39:39 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=67 Adjusted the support for the DEBUG_SCOPE within these so that ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=66 <div><strong>Rev 66 - dgisselq</strong> (2 file(s) modified)</div><div>Adjusted the support for the DEBUG_SCOPE within these so that ...</div>~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Thu, 22 Oct 2015 16:01:50 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=66 Lots of logic simplifications to the core, in addition to ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=65 <div><strong>Rev 65 - dgisselq</strong> (1 file(s) modified)</div><div>Lots of logic simplifications to the core, in addition to ...</div>~ /zipcpu/trunk/rtl/core/zipcpu.v<br /> dgisselq Thu, 22 Oct 2015 15:59:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2F&rev=65
© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.