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zipcpu WebSVN RSS feed - zipcpu https://opencores.org/websvn//websvn/listing?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F& Sun, 25 Sep 2022 05:42:47 +0100 FeedCreator 1.7.2 Adjusted the operator input line to reflect actual logic inputs, ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=87 <div><strong>Rev 87 - dgisselq</strong> (1 file(s) modified)</div><div>Adjusted the operator input line to reflect actual logic inputs, ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Sat, 02 Jan 2016 23:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=87 Removed the requirement to have the dev.scope.cpu hardware defined outside of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=86 <div><strong>Rev 86 - dgisselq</strong> (1 file(s) modified)</div><div>Removed the requirement to have the dev.scope.cpu hardware defined outside<br /> of ...</div>~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Sat, 02 Jan 2016 23:55:01 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=86 First check-in: the test bench for the divide instruction. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=77 <div><strong>Rev 77 - dgisselq</strong> (1 file(s) modified)</div><div>First check-in: the test bench for the divide instruction.</div>+ /zipcpu/trunk/bench/cpp/div_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:53:32 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=77 The biggest change here was to zippy_tb, to make it ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=76 <div><strong>Rev 76 - dgisselq</strong> (2 file(s) modified)</div><div>The biggest change here was to zippy_tb, to make it ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Mon, 28 Dec 2015 20:50:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=76 Modified for VLIW instructions. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=75 <div><strong>Rev 75 - dgisselq</strong> (1 file(s) modified)</div><div>Modified for VLIW instructions.</div>~ /zipcpu/trunk/bench/cpp/pdump.cpp<br /> dgisselq Mon, 28 Dec 2015 20:49:16 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=75 Added a bunch of debugging code to the Dhrystone benchmark ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=74 <div><strong>Rev 74 - dgisselq</strong> (4 file(s) modified)</div><div>Added a bunch of debugging code to the Dhrystone benchmark ...</div>~ /zipcpu/trunk/bench/asm/Makefile<br />+ /zipcpu/trunk/bench/asm/nullpc.s<br />+ /zipcpu/trunk/bench/asm/poptest.s<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Mon, 28 Dec 2015 20:48:36 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=74 This implements the &quot;new Instruction Set&quot; architecture for the Zip ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=69 <div><strong>Rev 69 - dgisselq</strong> (85 file(s) modified)</div><div>This implements the &quot;new Instruction Set&quot; architecture for the Zip ...</div>~ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/bench/asm/ivec.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/pcpc.S<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/twoc.cpp<br />~ /zipcpu/trunk/bench/cpp/twoc.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/gfx/bc.eps<br />~ /zipcpu/trunk/doc/gfx/bra.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.dia<br />~ /zipcpu/trunk/doc/gfx/cpu.eps<br />~ /zipcpu/trunk/doc/gfx/cpu.png<br />~ /zipcpu/trunk/doc/gfx/memrd.eps<br />~ /zipcpu/trunk/doc/gfx/memwr.eps<br />~ /zipcpu/trunk/doc/gfx/regset.png<br />~ /zipcpu/trunk/doc/gfx/system.dia<br />~ /zipcpu/trunk/doc/gfx/system.eps<br />~ /zipcpu/trunk/doc/gfx/system.png<br />~ /zipcpu/trunk/doc/gfx/zipbones.dia<br />~ /zipcpu/trunk/doc/gfx/zipbones.png<br />~ /zipcpu/trunk/doc/iset.html<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />~ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />~ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />+ /zipcpu/trunk/rtl/core/cpuops_deprecated.v<br />+ /zipcpu/trunk/rtl/core/div.v<br />+ /zipcpu/trunk/rtl/core/idecode.v<br />+ /zipcpu/trunk/rtl/core/idecode_deprecated.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />+ /zipcpu/trunk/rtl/core/pfcache.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/pipemem.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/cpudefs.v<br />~ /zipcpu/trunk/rtl/Makefile<br />~ /zipcpu/trunk/rtl/peripherals/flashcache.v<br />~ /zipcpu/trunk/rtl/peripherals/icontrol.v<br />~ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/wbwatchdog.v<br />~ /zipcpu/trunk/rtl/peripherals/zipcounter.v<br />~ /zipcpu/trunk/rtl/peripherals/zipjiffies.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptimer.v<br />~ /zipcpu/trunk/rtl/peripherals/ziptrap.v<br />~ /zipcpu/trunk/rtl/zipbones.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/lib/divs.S<br />~ /zipcpu/trunk/sw/lib/divu.S<br />~ /zipcpu/trunk/sw/lib/mpy32s.S<br />~ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/asmdata.h<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/optest.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/twoc.cpp<br />~ /zipcpu/trunk/sw/zasm/twoc.h<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.cpp<br />~ /zipcpu/trunk/sw/zasm/zopcodes.h<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.h<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br />~ /zipcpu/trunk/sw/zipdbg/devbus.h<br />~ /zipcpu/trunk/sw/zipdbg/regdefs.h<br />~ /zipcpu/trunk/sw/zipdbg/zipdbg.cpp<br />+ /zipcpu/trunk/zip.vim<br /> dgisselq Tue, 22 Dec 2015 16:06:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=69 Added a rudimentary profiling support to the simulator. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=58 <div><strong>Rev 58 - dgisselq</strong> (3 file(s) modified)</div><div>Added a rudimentary profiling support to the simulator.</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />+ /zipcpu/trunk/bench/cpp/pdump.cpp<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Thu, 22 Oct 2015 15:26:48 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=58 Some bug fixes to the dhrystone benchmark, and some compile ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=57 <div><strong>Rev 57 - dgisselq</strong> (3 file(s) modified)</div><div>Some bug fixes to the dhrystone benchmark, and some compile ...</div>~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Mon, 12 Oct 2015 13:30:15 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=57 Dhrystone benchmark updates--added the copyright notice. (Oops!) https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=50 <div><strong>Rev 50 - dgisselq</strong> (3 file(s) modified)</div><div>Dhrystone benchmark updates--added the copyright notice. (Oops!)</div>~ /zipcpu/trunk/bench/asm/Makefile<br />~ /zipcpu/trunk/bench/asm/testdiv.S<br />~ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Fri, 02 Oct 2015 21:53:44 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=50 Minor edits to the C++ testbench. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=43 <div><strong>Rev 43 - dgisselq</strong> (3 file(s) modified)</div><div>Minor edits to the C++ testbench.</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Fri, 02 Oct 2015 21:37:15 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=43 Oops -- forgot to add the stack. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=42 <div><strong>Rev 42 - dgisselq</strong> (1 file(s) modified)</div><div>Oops -- forgot to add the stack.</div>+ /zipcpu/trunk/bench/asm/stack.S<br /> dgisselq Fri, 02 Oct 2015 21:36:30 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=42 Assembly file for the Dhrystone benchmark added. https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=41 <div><strong>Rev 41 - dgisselq</strong> (4 file(s) modified)</div><div>Assembly file for the Dhrystone benchmark added.</div>- /zipcpu/trunk/bench/asm/lfsrleds.S<br />+ /zipcpu/trunk/bench/asm/Makefile<br />+ /zipcpu/trunk/bench/asm/testdiv.S<br />+ /zipcpu/trunk/bench/asm/zipdhry.S<br /> dgisselq Fri, 02 Oct 2015 21:35:49 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=41 Quick update, updates the assembly for the new version of ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=40 <div><strong>Rev 40 - dgisselq</strong> (1 file(s) modified)</div><div>Quick update, updates the assembly for the new version of ...</div>~ /zipcpu/trunk/bench/asm/wdt.S<br /> dgisselq Fri, 02 Oct 2015 21:33:06 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=40 Here's the documentation update to support the pipelined read/writes of the ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=39 <div><strong>Rev 39 - dgisselq</strong> (5 file(s) modified)</div><div>Here's the documentation update to support the pipelined read/writes of<br /> the ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/sw/zasm/test.S<br /> dgisselq Tue, 29 Sep 2015 18:48:13 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=39 *Lots* of changes to increase processing speed and remove pipeline ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=36 <div><strong>Rev 36 - dgisselq</strong> (34 file(s) modified)</div><div>*Lots* of changes to increase processing speed and remove pipeline ...</div>+ /zipcpu/trunk/bench/asm/lfsrleds.S<br />~ /zipcpu/trunk/bench/asm/lodsto.S<br />~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/memsim.cpp<br />~ /zipcpu/trunk/bench/cpp/memsim.h<br />~ /zipcpu/trunk/bench/cpp/testb.h<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />+ /zipcpu/trunk/doc/gfx/zippipe.dia<br />~ /zipcpu/trunk/doc/Makefile<br />~ /zipcpu/trunk/doc/spec.pdf<br />~ /zipcpu/trunk/doc/src/spec.tex<br />~ /zipcpu/trunk/Makefile<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/aux/wbarbiter.v<br />+ /zipcpu/trunk/rtl/aux/wbdblpriarb.v<br />+ /zipcpu/trunk/rtl/aux/wbpriarbiter.v<br />~ /zipcpu/trunk/rtl/core/memops.v<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/core/prefetch.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/Makefile<br />+ /zipcpu/trunk/rtl/peripherals/wbdmac.v<br />+ /zipcpu/trunk/rtl/peripherals/zipport.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />+ /zipcpu/trunk/sw/lib<br />+ /zipcpu/trunk/sw/lib/divs.S<br />+ /zipcpu/trunk/sw/lib/divu.S<br />+ /zipcpu/trunk/sw/lib/mpy32s.S<br />+ /zipcpu/trunk/sw/lib/mpy32u.S<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br /> dgisselq Sun, 20 Sep 2015 13:09:46 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=36 Bunches of changes, although very little changed with the core ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=34 <div><strong>Rev 34 - dgisselq</strong> (11 file(s) modified)</div><div>Bunches of changes, although very little changed with the core ...</div>~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/aux/busdelay.v<br />~ /zipcpu/trunk/rtl/core/zipcpu.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br />~ /zipcpu/trunk/sw/zasm/asmdata.cpp<br />~ /zipcpu/trunk/sw/zasm/Makefile<br />~ /zipcpu/trunk/sw/zasm/sys.i<br />~ /zipcpu/trunk/sw/zasm/test.S<br />~ /zipcpu/trunk/sw/zasm/zasm.l<br />~ /zipcpu/trunk/sw/zasm/zasm.y<br />~ /zipcpu/trunk/sw/zasm/zpp.l<br /> dgisselq Tue, 25 Aug 2015 18:29:20 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=34 The big change to the test bench code in this ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=27 <div><strong>Rev 27 - dgisselq</strong> (2 file(s) modified)</div><div>The big change to the test bench code in this ...</div>~ /zipcpu/trunk/bench/cpp/Makefile<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br /> dgisselq Sat, 22 Aug 2015 01:27:51 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=27 Bunch of changes while trying to get a hello world ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=12 <div><strong>Rev 12 - dgisselq</strong> (4 file(s) modified)</div><div>Bunch of changes while trying to get a hello world ...</div>+ /zipcpu/trunk/bench/asm/helloworld.S<br />~ /zipcpu/trunk/rtl/core/cpuops.v<br />~ /zipcpu/trunk/sw/zasm/zdump.cpp<br />~ /zipcpu/trunk/sw/zasm/zparser.cpp<br /> dgisselq Tue, 28 Jul 2015 20:12:12 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=12 This version works on an FPGA!!! (Or at least the wdt.S ... https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=11 <div><strong>Rev 11 - dgisselq</strong> (5 file(s) modified)</div><div>This version works on an FPGA!!!<br /> <br /> (Or at least the wdt.S ...</div>+ /zipcpu/trunk/bench/asm/lfsr.S<br />~ /zipcpu/trunk/bench/asm/wdt.S<br />~ /zipcpu/trunk/bench/cpp/zippy_tb.cpp<br />~ /zipcpu/trunk/rtl/core/pipefetch.v<br />~ /zipcpu/trunk/rtl/zipsystem.v<br /> dgisselq Tue, 28 Jul 2015 11:53:26 +0100 https://opencores.org/websvn//websvn/revision?repname=zipcpu&path=%2Fzipcpu%2Ftrunk%2Fbench%2F&rev=11
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